configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
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   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
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  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
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  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39
  40 from __future__ import print_function
  41 from __future__ import absolute_import
  42
  43 import m5
  44 from m5.objects import *
  45 from m5.util import *
  46 from common.Benchmarks import *
  47 from common import ObjectList
  48
  49 # Populate to reflect supported os types per target ISA
  50 os_types = { 'mips'  : [ 'linux' ],
  51              'sparc' : [ 'linux' ],
  52              'x86'   : [ 'linux' ],
  53              'arm'   : [ 'linux',
  54                          'android-gingerbread',
  55                          'android-ics',
  56                          'android-jellybean',
  57                          'android-kitkat',
  58                          'android-nougat', ],
  59            }
  60
  61 class CowIdeDisk(IdeDisk):
  62     image = CowDiskImage(child=RawDiskImage(read_only=True),
  63                          read_only=False)
  64
  65     def childImage(self, ci):
  66         self.image.child.image_file = ci
  67
  68 class MemBus(SystemXBar):
  69     badaddr_responder = BadAddr()
  70     default = Self.badaddr_responder.pio
  71
  72 def attach_9p(parent, bus):
  73     viopci = PciVirtIO()
  74     viopci.vio = VirtIO9PDiod()
  75     viodir = os.path.join(m5.options.outdir, '9p')
  76     viopci.vio.root = os.path.join(viodir, 'share')
  77     viopci.vio.socketPath = os.path.join(viodir, 'socket')
  78     if not os.path.exists(viopci.vio.root):
  79         os.makedirs(viopci.vio.root)
  80     if os.path.exists(viopci.vio.socketPath):
  81         os.remove(viopci.vio.socketPath)
  82     parent.viopci = viopci
  83     parent.attachPciDevice(viopci, bus)
  84
  85 def fillInCmdline(mdesc, template, **kwargs):
  86     kwargs.setdefault('rootdev', mdesc.rootdev())
  87     kwargs.setdefault('mem', mdesc.mem())
  88     kwargs.setdefault('script', mdesc.script())
  89     return template % kwargs
  90
  91 def makeCowDisks(disk_paths):
  92     disks = []
  93     for disk_path in disk_paths:
  94         disk = CowIdeDisk(driveID='master')
  95         disk.childImage(disk_path);
  96         disks.append(disk)
  97     return disks
  98
  99 def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
 100     # Constants from iob.cc and uart8250.cc
 101     iob_man_addr = 0x9800000000
 102     uart_pio_size = 8
 103
 104     class CowMmDisk(MmDisk):
 105         image = CowDiskImage(child=RawDiskImage(read_only=True),
 106                              read_only=False)
 107
 108         def childImage(self, ci):
 109             self.image.child.image_file = ci
 110
 111     self = SparcSystem()
 112     if not mdesc:
 113         # generic system
 114         mdesc = SysConfig()
 115     self.readfile = mdesc.script()
 116     self.iobus = IOXBar()
 117     self.membus = MemBus()
 118     self.bridge = Bridge(delay='50ns')
 119     self.t1000 = T1000()
 120     self.t1000.attachOnChipIO(self.membus)
 121     self.t1000.attachIO(self.iobus)
 122     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 123                        AddrRange(Addr('2GB'), size ='256MB')]
 124     self.bridge.master = self.iobus.slave
 125     self.bridge.slave = self.membus.master
 126     self.intrctrl = IntrControl()
 127     self.disk0 = CowMmDisk()
 128     self.disk0.childImage(mdesc.disks()[0])
 129     self.disk0.pio = self.iobus.master
 130
 131     # The puart0 and hvuart are placed on the IO bus, so create ranges
 132     # for them. The remaining IO range is rather fragmented, so poke
 133     # holes for the iob and partition descriptors etc.
 134     self.bridge.ranges = \
 135         [
 136         AddrRange(self.t1000.puart0.pio_addr,
 137                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 138         AddrRange(self.disk0.pio_addr,
 139                   self.t1000.fake_jbi.pio_addr +
 140                   self.t1000.fake_jbi.pio_size - 1),
 141         AddrRange(self.t1000.fake_clk.pio_addr,
 142                   iob_man_addr - 1),
 143         AddrRange(self.t1000.fake_l2_1.pio_addr,
 144                   self.t1000.fake_ssi.pio_addr +
 145                   self.t1000.fake_ssi.pio_size - 1),
 146         AddrRange(self.t1000.hvuart.pio_addr,
 147                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 148         ]
 149
 150     workload = SparcFsWorkload()
 151
 152     # ROM for OBP/Reset/Hypervisor
 153     self.rom = SimpleMemory(image_file=binary('t1000_rom.bin'),
 154             range=AddrRange(0xfff0000000, size='8MB'))
 155     # nvram
 156     self.nvram = SimpleMemory(image_file=binary('nvram1'),
 157             range=AddrRange(0x1f11000000, size='8kB'))
 158     # hypervisor description
 159     self.hypervisor_desc = SimpleMemory(image_file=binary('1up-hv.bin'),
 160             range=AddrRange(0x1f12080000, size='8kB'))
 161     # partition description
 162     self.partition_desc = SimpleMemory(image_file=binary('1up-md.bin'),
 163             range=AddrRange(0x1f12000000, size='8kB'))
 164
 165     self.rom.port = self.membus.master
 166     self.nvram.port = self.membus.master
 167     self.hypervisor_desc.port = self.membus.master
 168     self.partition_desc.port = self.membus.master
 169
 170     self.system_port = self.membus.slave
 171
 172     self.workload = workload
 173
 174     return self
 175
 176 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 177                   dtb_filename=None, bare_metal=False, cmdline=None,
 178                   external_memory="", ruby=False, security=False,
 179                   vio_9p=None, bootloader=None):
 180     assert machine_type
 181
 182     pci_devices = []
 183
 184     self = ArmSystem()
 185
 186     if not mdesc:
 187         # generic system
 188         mdesc = SysConfig()
 189
 190     self.readfile = mdesc.script()
 191     self.iobus = IOXBar()
 192     if not ruby:
 193         self.bridge = Bridge(delay='50ns')
 194         self.bridge.master = self.iobus.slave
 195         self.membus = MemBus()
 196         self.membus.badaddr_responder.warn_access = "warn"
 197         self.bridge.slave = self.membus.master
 198
 199     self.mem_mode = mem_mode
 200
 201     platform_class = ObjectList.platform_list.get(machine_type)
 202     # Resolve the real platform name, the original machine_type
 203     # variable might have been an alias.
 204     machine_type = platform_class.__name__
 205     self.realview = platform_class()
 206     self._bootmem = self.realview.bootmem
 207
 208     # Attach any PCI devices this platform supports
 209     self.realview.attachPciDevices()
 210
 211     disks = makeCowDisks(mdesc.disks())
 212     # Old platforms have a built-in IDE or CF controller. Default to
 213     # the IDE controller if both exist. New platforms expect the
 214     # storage controller to be added from the config script.
 215     if hasattr(self.realview, "ide"):
 216         self.realview.ide.disks = disks
 217     elif hasattr(self.realview, "cf_ctrl"):
 218         self.realview.cf_ctrl.disks = disks
 219     else:
 220         self.pci_ide = IdeController(disks=disks)
 221         pci_devices.append(self.pci_ide)
 222
 223     self.mem_ranges = []
 224     size_remain = long(Addr(mdesc.mem()))
 225     for region in self.realview._mem_regions:
 226         if size_remain > long(region.size()):
 227             self.mem_ranges.append(region)
 228             size_remain = size_remain - long(region.size())
 229         else:
 230             self.mem_ranges.append(AddrRange(region.start, size=size_remain))
 231             size_remain = 0
 232             break
 233         warn("Memory size specified spans more than one region. Creating" \
 234              " another memory controller for that range.")
 235
 236     if size_remain > 0:
 237         fatal("The currently selected ARM platforms doesn't support" \
 238               " the amount of DRAM you've selected. Please try" \
 239               " another platform")
 240
 241     self.have_security = security
 242
 243     if bare_metal:
 244         # EOT character on UART will end the simulation
 245         self.realview.uart[0].end_on_eot = True
 246         self.workload = ArmFsWorkload(atags_addr=0)
 247     else:
 248         workload = ArmFsLinux()
 249
 250         if dtb_filename:
 251             workload.dtb_filename = binary(dtb_filename)
 252
 253         workload.machine_type = \
 254             machine_type if machine_type in ArmMachineType.map else "DTOnly"
 255
 256         # Ensure that writes to the UART actually go out early in the boot
 257         if not cmdline:
 258             cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
 259                       'lpj=19988480 norandmaps rw loglevel=8 ' + \
 260                       'mem=%(mem)s root=%(rootdev)s'
 261
 262         if hasattr(self.realview.gic, 'cpu_addr'):
 263             self.gic_cpu_addr = self.realview.gic.cpu_addr
 264
 265         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 266
 267         # This check is for users who have previously put 'android' in
 268         # the disk image filename to tell the config scripts to
 269         # prepare the kernel with android-specific boot options. That
 270         # behavior has been replaced with a more explicit option per
 271         # the error message below. The disk can have any name now and
 272         # doesn't need to include 'android' substring.
 273         if (mdesc.disks() and
 274                 os.path.split(mdesc.disks()[0])[-1].lower().count('android')):
 275             if 'android' not in mdesc.os_type():
 276                 fatal("It looks like you are trying to boot an Android " \
 277                       "platform.  To boot Android, you must specify " \
 278                       "--os-type with an appropriate Android release on " \
 279                       "the command line.")
 280
 281         # android-specific tweaks
 282         if 'android' in mdesc.os_type():
 283             # generic tweaks
 284             cmdline += " init=/init"
 285
 286             # release-specific tweaks
 287             if 'kitkat' in mdesc.os_type():
 288                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 289                            "android.bootanim=0 "
 290             elif 'nougat' in mdesc.os_type():
 291                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 292                            "android.bootanim=0 " + \
 293                            "vmalloc=640MB " + \
 294                            "android.early.fstab=/fstab.gem5 " + \
 295                            "androidboot.selinux=permissive " + \
 296                            "video=Virtual-1:1920x1080-16"
 297
 298         workload.command_line = fillInCmdline(mdesc, cmdline)
 299
 300         self.workload = workload
 301
 302         self.realview.setupBootLoader(self, binary, bootloader)
 303
 304     if external_memory:
 305         # I/O traffic enters iobus
 306         self.external_io = ExternalMaster(port_data="external_io",
 307                                           port_type=external_memory)
 308         self.external_io.port = self.iobus.slave
 309
 310         # Ensure iocache only receives traffic destined for (actual) memory.
 311         self.iocache = ExternalSlave(port_data="iocache",
 312                                      port_type=external_memory,
 313                                      addr_ranges=self.mem_ranges)
 314         self.iocache.port = self.iobus.master
 315
 316         # Let system_port get to nvmem and nothing else.
 317         self.bridge.ranges = [self.realview.nvmem.range]
 318
 319         self.realview.attachOnChipIO(self.iobus)
 320         # Attach off-chip devices
 321         self.realview.attachIO(self.iobus)
 322     elif ruby:
 323         self._dma_ports = [ ]
 324         self._mem_ports = [ ]
 325         self.realview.attachOnChipIO(self.iobus,
 326             dma_ports=self._dma_ports, mem_ports=self._mem_ports)
 327         self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
 328     else:
 329         self.realview.attachOnChipIO(self.membus, self.bridge)
 330         # Attach off-chip devices
 331         self.realview.attachIO(self.iobus)
 332
 333     for dev in pci_devices:
 334         self.realview.attachPciDevice(
 335             dev, self.iobus,
 336             dma_ports=self._dma_ports if ruby else None)
 337
 338     self.intrctrl = IntrControl()
 339     self.terminal = Terminal()
 340     self.vncserver = VncServer()
 341
 342     if vio_9p:
 343         attach_9p(self.realview, self.iobus)
 344
 345     if not ruby:
 346         self.system_port = self.membus.slave
 347
 348     if ruby:
 349         if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
 350             fatal("The MI_example protocol cannot implement Load/Store "
 351                   "Exclusive operations. Multicore ARM systems configured "
 352                   "with the MI_example protocol will not work properly.")
 353         warn("You are trying to use Ruby on ARM, which is not working "
 354              "properly yet.")
 355
 356     return self
 357
 358
 359 def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
 360     class BaseMalta(Malta):
 361         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 362         ide = IdeController(disks=Parent.disks,
 363                             pci_func=0, pci_dev=0, pci_bus=0)
 364
 365     self = LinuxMipsSystem()
 366     if not mdesc:
 367         # generic system
 368         mdesc = SysConfig()
 369     self.readfile = mdesc.script()
 370     self.iobus = IOXBar()
 371     self.membus = MemBus()
 372     self.bridge = Bridge(delay='50ns')
 373     self.mem_ranges = [AddrRange('1GB')]
 374     self.bridge.master = self.iobus.slave
 375     self.bridge.slave = self.membus.master
 376     self.disks = makeCowDisks(mdesc.disks())
 377     self.malta = BaseMalta()
 378     self.malta.attachIO(self.iobus)
 379     self.malta.ide.pio = self.iobus.master
 380     self.malta.ide.dma = self.iobus.slave
 381     self.malta.ethernet.pio = self.iobus.master
 382     self.malta.ethernet.dma = self.iobus.slave
 383     self.simple_disk = SimpleDisk(disk=RawDiskImage(
 384         image_file = mdesc.disks()[0], read_only = True))
 385     self.intrctrl = IntrControl()
 386     self.mem_mode = mem_mode
 387     self.terminal = Terminal()
 388     self.console = binary('mips/console')
 389     if not cmdline:
 390         cmdline = 'root=/dev/hda1 console=ttyS0'
 391     self.workload = OsKernel(command_line=fillInCmdline(mdesc, cmdline))
 392
 393     self.system_port = self.membus.slave
 394
 395     return self
 396
 397 def x86IOAddress(port):
 398     IO_address_space_base = 0x8000000000000000
 399     return IO_address_space_base + port
 400
 401 def connectX86ClassicSystem(x86_sys, numCPUs):
 402     # Constants similar to x86_traits.hh
 403     IO_address_space_base = 0x8000000000000000
 404     pci_config_address_space_base = 0xc000000000000000
 405     interrupts_address_space_base = 0xa000000000000000
 406     APIC_range_size = 1 << 12;
 407
 408     x86_sys.membus = MemBus()
 409
 410     # North Bridge
 411     x86_sys.iobus = IOXBar()
 412     x86_sys.bridge = Bridge(delay='50ns')
 413     x86_sys.bridge.master = x86_sys.iobus.slave
 414     x86_sys.bridge.slave = x86_sys.membus.master
 415     # Allow the bridge to pass through:
 416     #  1) kernel configured PCI device memory map address: address range
 417     #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
 418     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
 419     #  3) everything in the IO address range up to the local APIC, and
 420     #  4) then the entire PCI address space and beyond.
 421     x86_sys.bridge.ranges = \
 422         [
 423         AddrRange(0xC0000000, 0xFFFF0000),
 424         AddrRange(IO_address_space_base,
 425                   interrupts_address_space_base - 1),
 426         AddrRange(pci_config_address_space_base,
 427                   Addr.max)
 428         ]
 429
 430     # Create a bridge from the IO bus to the memory bus to allow access to
 431     # the local APIC (two pages)
 432     x86_sys.apicbridge = Bridge(delay='50ns')
 433     x86_sys.apicbridge.slave = x86_sys.iobus.master
 434     x86_sys.apicbridge.master = x86_sys.membus.slave
 435     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 436                                            interrupts_address_space_base +
 437                                            numCPUs * APIC_range_size
 438                                            - 1)]
 439
 440     # connect the io bus
 441     x86_sys.pc.attachIO(x86_sys.iobus)
 442
 443     x86_sys.system_port = x86_sys.membus.slave
 444
 445 def connectX86RubySystem(x86_sys):
 446     # North Bridge
 447     x86_sys.iobus = IOXBar()
 448
 449     # add the ide to the list of dma devices that later need to attach to
 450     # dma controllers
 451     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 452     x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
 453
 454
 455 def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None, Ruby=False):
 456     self = X86System()
 457
 458     if workload is None:
 459         workload = X86FsWorkload()
 460     self.workload = workload
 461
 462     if not mdesc:
 463         # generic system
 464         mdesc = SysConfig()
 465     self.readfile = mdesc.script()
 466
 467     self.mem_mode = mem_mode
 468
 469     # Physical memory
 470     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
 471     # for various devices.  Hence, if the physical memory size is greater than
 472     # 3GB, we need to split it into two parts.
 473     excess_mem_size = \
 474         convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
 475     if excess_mem_size <= 0:
 476         self.mem_ranges = [AddrRange(mdesc.mem())]
 477     else:
 478         warn("Physical memory size specified is %s which is greater than " \
 479              "3GB.  Twice the number of memory controllers would be " \
 480              "created."  % (mdesc.mem()))
 481
 482         self.mem_ranges = [AddrRange('3GB'),
 483             AddrRange(Addr('4GB'), size = excess_mem_size)]
 484
 485     # Platform
 486     self.pc = Pc()
 487
 488     # Create and connect the busses required by each memory system
 489     if Ruby:
 490         connectX86RubySystem(self)
 491     else:
 492         connectX86ClassicSystem(self, numCPUs)
 493
 494     self.intrctrl = IntrControl()
 495
 496     # Disks
 497     disks = makeCowDisks(mdesc.disks())
 498     self.pc.south_bridge.ide.disks = disks
 499
 500     # Add in a Bios information structure.
 501     structures = [X86SMBiosBiosInformation()]
 502     workload.smbios_table.structures = structures
 503
 504     # Set up the Intel MP table
 505     base_entries = []
 506     ext_entries = []
 507     for i in range(numCPUs):
 508         bp = X86IntelMPProcessor(
 509                 local_apic_id = i,
 510                 local_apic_version = 0x14,
 511                 enable = True,
 512                 bootstrap = (i == 0))
 513         base_entries.append(bp)
 514     io_apic = X86IntelMPIOAPIC(
 515             id = numCPUs,
 516             version = 0x11,
 517             enable = True,
 518             address = 0xfec00000)
 519     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 520     base_entries.append(io_apic)
 521     # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 522     # but linux kernel cannot config PCI device if it was not connected to
 523     # PCI bus, so we fix PCI bus id to 0, and ISA bus id to 1.
 524     pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
 525     base_entries.append(pci_bus)
 526     isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
 527     base_entries.append(isa_bus)
 528     connect_busses = X86IntelMPBusHierarchy(bus_id=1,
 529             subtractive_decode=True, parent_bus=0)
 530     ext_entries.append(connect_busses)
 531     pci_dev4_inta = X86IntelMPIOIntAssignment(
 532             interrupt_type = 'INT',
 533             polarity = 'ConformPolarity',
 534             trigger = 'ConformTrigger',
 535             source_bus_id = 0,
 536             source_bus_irq = 0 + (4 << 2),
 537             dest_io_apic_id = io_apic.id,
 538             dest_io_apic_intin = 16)
 539     base_entries.append(pci_dev4_inta)
 540     def assignISAInt(irq, apicPin):
 541         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 542                 interrupt_type = 'ExtInt',
 543                 polarity = 'ConformPolarity',
 544                 trigger = 'ConformTrigger',
 545                 source_bus_id = 1,
 546                 source_bus_irq = irq,
 547                 dest_io_apic_id = io_apic.id,
 548                 dest_io_apic_intin = 0)
 549         base_entries.append(assign_8259_to_apic)
 550         assign_to_apic = X86IntelMPIOIntAssignment(
 551                 interrupt_type = 'INT',
 552                 polarity = 'ConformPolarity',
 553                 trigger = 'ConformTrigger',
 554                 source_bus_id = 1,
 555                 source_bus_irq = irq,
 556                 dest_io_apic_id = io_apic.id,
 557                 dest_io_apic_intin = apicPin)
 558         base_entries.append(assign_to_apic)
 559     assignISAInt(0, 2)
 560     assignISAInt(1, 1)
 561     for i in range(3, 15):
 562         assignISAInt(i, i)
 563     workload.intel_mp_table.base_entries = base_entries
 564     workload.intel_mp_table.ext_entries = ext_entries
 565
 566     return self
 567
 568 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
 569                        cmdline=None):
 570     # Build up the x86 system and then specialize it for Linux
 571     self = makeX86System(mem_mode, numCPUs, mdesc, X86FsLinux(), Ruby)
 572
 573     # We assume below that there's at least 1MB of memory. We'll require 2
 574     # just to avoid corner cases.
 575     phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
 576     assert(phys_mem_size >= 0x200000)
 577     assert(len(self.mem_ranges) <= 2)
 578
 579     entries = \
 580        [
 581         # Mark the first megabyte of memory as reserved
 582         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 583         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 584         # Mark the rest of physical memory as available
 585         X86E820Entry(addr = 0x100000,
 586                 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
 587                 range_type = 1),
 588         ]
 589
 590     # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
 591     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
 592     # specific range can pass though bridge to iobus.
 593     if len(self.mem_ranges) == 1:
 594         entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
 595             size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
 596             range_type=2))
 597
 598     # Reserve the last 16kB of the 32-bit address space for the m5op interface
 599     entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
 600
 601     # In case the physical memory is greater than 3GB, we split it into two
 602     # parts and add a separate e820 entry for the second part.  This entry
 603     # starts at 0x100000000,  which is the first address after the space
 604     # reserved for devices.
 605     if len(self.mem_ranges) == 2:
 606         entries.append(X86E820Entry(addr = 0x100000000,
 607             size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
 608
 609     self.workload.e820_table.entries = entries
 610
 611     # Command line
 612     if not cmdline:
 613         cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
 614     self.workload.command_line = fillInCmdline(mdesc, cmdline)
 615     return self
 616
 617
 618 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 619     self = Root(full_system = full_system)
 620     self.testsys = testSystem
 621     self.drivesys = driveSystem
 622     self.etherlink = EtherLink()
 623
 624     if hasattr(testSystem, 'realview'):
 625         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 626         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 627     elif hasattr(testSystem, 'tsunami'):
 628         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 629         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 630     else:
 631         fatal("Don't know how to connect these system together")
 632
 633     if dumpfile:
 634         self.etherdump = EtherDump(file=dumpfile)
 635         self.etherlink.dump = Parent.etherdump
 636
 637     return self
 638
 639
 640 def makeDistRoot(testSystem,
 641                  rank,
 642                  size,
 643                  server_name,
 644                  server_port,
 645                  sync_repeat,
 646                  sync_start,
 647                  linkspeed,
 648                  linkdelay,
 649                  dumpfile):
 650     self = Root(full_system = True)
 651     self.testsys = testSystem
 652
 653     self.etherlink = DistEtherLink(speed = linkspeed,
 654                                    delay = linkdelay,
 655                                    dist_rank = rank,
 656                                    dist_size = size,
 657                                    server_name = server_name,
 658                                    server_port = server_port,
 659                                    sync_start = sync_start,
 660                                    sync_repeat = sync_repeat)
 661
 662     if hasattr(testSystem, 'realview'):
 663         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 664     elif hasattr(testSystem, 'tsunami'):
 665         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 666     else:
 667         fatal("Don't know how to connect DistEtherLink to this system")
 668
 669     if dumpfile:
 670         self.etherdump = EtherDump(file=dumpfile)
 671         self.etherlink.dump = Parent.etherdump
 672
 673     return self