configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
   2 # Copyright (c) 2020 Barkhausen Institut
   3 # All rights reserved.
   4 #
   5 # The license below extends only to copyright in the software and shall
   6 # not be construed as granting a license to any other intellectual
   7 # property including but not limited to intellectual property relating
   8 # to a hardware implementation of the functionality of the software
   9 # licensed hereunder.  You may use the software subject to the license
  10 # terms below provided that you ensure that this notice is replicated
  11 # unmodified and in its entirety in all distributions of the software,
  12 # modified or unmodified, in source code or in binary form.
  13 #
  14 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  15 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  16 # All rights reserved.
  17 #
  18 # Redistribution and use in source and binary forms, with or without
  19 # modification, are permitted provided that the following conditions are
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  27 # this software without specific prior written permission.
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  39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40
  41 from __future__ import print_function
  42 from __future__ import absolute_import
  43
  44 import six
  45
  46 import m5
  47 from m5.objects import *
  48 from m5.util import *
  49 from common.Benchmarks import *
  50 from common import ObjectList
  51
  52 if six.PY3:
  53     long = int
  54
  55 # Populate to reflect supported os types per target ISA
  56 os_types = { 'mips'  : [ 'linux' ],
  57              'riscv' : [ 'linux' ], # TODO that's a lie
  58              'sparc' : [ 'linux' ],
  59              'x86'   : [ 'linux' ],
  60              'arm'   : [ 'linux',
  61                          'android-gingerbread',
  62                          'android-ics',
  63                          'android-jellybean',
  64                          'android-kitkat',
  65                          'android-nougat', ],
  66            }
  67
  68 class CowIdeDisk(IdeDisk):
  69     image = CowDiskImage(child=RawDiskImage(read_only=True),
  70                          read_only=False)
  71
  72     def childImage(self, ci):
  73         self.image.child.image_file = ci
  74
  75 class MemBus(SystemXBar):
  76     badaddr_responder = BadAddr()
  77     default = Self.badaddr_responder.pio
  78
  79 def attach_9p(parent, bus):
  80     viopci = PciVirtIO()
  81     viopci.vio = VirtIO9PDiod()
  82     viodir = os.path.join(m5.options.outdir, '9p')
  83     viopci.vio.root = os.path.join(viodir, 'share')
  84     viopci.vio.socketPath = os.path.join(viodir, 'socket')
  85     if not os.path.exists(viopci.vio.root):
  86         os.makedirs(viopci.vio.root)
  87     if os.path.exists(viopci.vio.socketPath):
  88         os.remove(viopci.vio.socketPath)
  89     parent.viopci = viopci
  90     parent.attachPciDevice(viopci, bus)
  91
  92 def fillInCmdline(mdesc, template, **kwargs):
  93     kwargs.setdefault('rootdev', mdesc.rootdev())
  94     kwargs.setdefault('mem', mdesc.mem())
  95     kwargs.setdefault('script', mdesc.script())
  96     return template % kwargs
  97
  98 def makeCowDisks(disk_paths):
  99     disks = []
 100     for disk_path in disk_paths:
 101         disk = CowIdeDisk(driveID='master')
 102         disk.childImage(disk_path);
 103         disks.append(disk)
 104     return disks
 105
 106 def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
 107     # Constants from iob.cc and uart8250.cc
 108     iob_man_addr = 0x9800000000
 109     uart_pio_size = 8
 110
 111     class CowMmDisk(MmDisk):
 112         image = CowDiskImage(child=RawDiskImage(read_only=True),
 113                              read_only=False)
 114
 115         def childImage(self, ci):
 116             self.image.child.image_file = ci
 117
 118     self = System()
 119     if not mdesc:
 120         # generic system
 121         mdesc = SysConfig()
 122     self.readfile = mdesc.script()
 123     self.iobus = IOXBar()
 124     self.membus = MemBus()
 125     self.bridge = Bridge(delay='50ns')
 126     self.t1000 = T1000()
 127     self.t1000.attachOnChipIO(self.membus)
 128     self.t1000.attachIO(self.iobus)
 129     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 130                        AddrRange(Addr('2GB'), size ='256MB')]
 131     self.bridge.master = self.iobus.slave
 132     self.bridge.slave = self.membus.master
 133     self.intrctrl = IntrControl()
 134     self.disk0 = CowMmDisk()
 135     self.disk0.childImage(mdesc.disks()[0])
 136     self.disk0.pio = self.iobus.master
 137
 138     # The puart0 and hvuart are placed on the IO bus, so create ranges
 139     # for them. The remaining IO range is rather fragmented, so poke
 140     # holes for the iob and partition descriptors etc.
 141     self.bridge.ranges = \
 142         [
 143         AddrRange(self.t1000.puart0.pio_addr,
 144                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 145         AddrRange(self.disk0.pio_addr,
 146                   self.t1000.fake_jbi.pio_addr +
 147                   self.t1000.fake_jbi.pio_size - 1),
 148         AddrRange(self.t1000.fake_clk.pio_addr,
 149                   iob_man_addr - 1),
 150         AddrRange(self.t1000.fake_l2_1.pio_addr,
 151                   self.t1000.fake_ssi.pio_addr +
 152                   self.t1000.fake_ssi.pio_size - 1),
 153         AddrRange(self.t1000.hvuart.pio_addr,
 154                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 155         ]
 156
 157     workload = SparcFsWorkload()
 158
 159     # ROM for OBP/Reset/Hypervisor
 160     self.rom = SimpleMemory(image_file=binary('t1000_rom.bin'),
 161             range=AddrRange(0xfff0000000, size='8MB'))
 162     # nvram
 163     self.nvram = SimpleMemory(image_file=binary('nvram1'),
 164             range=AddrRange(0x1f11000000, size='8kB'))
 165     # hypervisor description
 166     self.hypervisor_desc = SimpleMemory(image_file=binary('1up-hv.bin'),
 167             range=AddrRange(0x1f12080000, size='8kB'))
 168     # partition description
 169     self.partition_desc = SimpleMemory(image_file=binary('1up-md.bin'),
 170             range=AddrRange(0x1f12000000, size='8kB'))
 171
 172     self.rom.port = self.membus.master
 173     self.nvram.port = self.membus.master
 174     self.hypervisor_desc.port = self.membus.master
 175     self.partition_desc.port = self.membus.master
 176
 177     self.system_port = self.membus.slave
 178
 179     self.workload = workload
 180
 181     return self
 182
 183 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 184                   dtb_filename=None, bare_metal=False, cmdline=None,
 185                   external_memory="", ruby=False, security=False,
 186                   vio_9p=None, bootloader=None):
 187     assert machine_type
 188
 189     pci_devices = []
 190
 191     self = ArmSystem()
 192
 193     if not mdesc:
 194         # generic system
 195         mdesc = SysConfig()
 196
 197     self.readfile = mdesc.script()
 198     self.iobus = IOXBar()
 199     if not ruby:
 200         self.bridge = Bridge(delay='50ns')
 201         self.bridge.master = self.iobus.slave
 202         self.membus = MemBus()
 203         self.membus.badaddr_responder.warn_access = "warn"
 204         self.bridge.slave = self.membus.master
 205
 206     self.mem_mode = mem_mode
 207
 208     platform_class = ObjectList.platform_list.get(machine_type)
 209     # Resolve the real platform name, the original machine_type
 210     # variable might have been an alias.
 211     machine_type = platform_class.__name__
 212     self.realview = platform_class()
 213     self._bootmem = self.realview.bootmem
 214
 215     # Attach any PCI devices this platform supports
 216     self.realview.attachPciDevices()
 217
 218     disks = makeCowDisks(mdesc.disks())
 219     # Old platforms have a built-in IDE or CF controller. Default to
 220     # the IDE controller if both exist. New platforms expect the
 221     # storage controller to be added from the config script.
 222     if hasattr(self.realview, "ide"):
 223         self.realview.ide.disks = disks
 224     elif hasattr(self.realview, "cf_ctrl"):
 225         self.realview.cf_ctrl.disks = disks
 226     else:
 227         self.pci_ide = IdeController(disks=disks)
 228         pci_devices.append(self.pci_ide)
 229
 230     self.mem_ranges = []
 231     size_remain = long(Addr(mdesc.mem()))
 232     for region in self.realview._mem_regions:
 233         if size_remain > long(region.size()):
 234             self.mem_ranges.append(region)
 235             size_remain = size_remain - long(region.size())
 236         else:
 237             self.mem_ranges.append(AddrRange(region.start, size=size_remain))
 238             size_remain = 0
 239             break
 240         warn("Memory size specified spans more than one region. Creating" \
 241              " another memory controller for that range.")
 242
 243     if size_remain > 0:
 244         fatal("The currently selected ARM platforms doesn't support" \
 245               " the amount of DRAM you've selected. Please try" \
 246               " another platform")
 247
 248     self.have_security = security
 249
 250     if bare_metal:
 251         # EOT character on UART will end the simulation
 252         self.realview.uart[0].end_on_eot = True
 253         self.workload = ArmFsWorkload(atags_addr=0)
 254     else:
 255         workload = ArmFsLinux()
 256
 257         if dtb_filename:
 258             workload.dtb_filename = binary(dtb_filename)
 259
 260         workload.machine_type = \
 261             machine_type if machine_type in ArmMachineType.map else "DTOnly"
 262
 263         # Ensure that writes to the UART actually go out early in the boot
 264         if not cmdline:
 265             cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
 266                       'lpj=19988480 norandmaps rw loglevel=8 ' + \
 267                       'mem=%(mem)s root=%(rootdev)s'
 268
 269         if hasattr(self.realview.gic, 'cpu_addr'):
 270             self.gic_cpu_addr = self.realview.gic.cpu_addr
 271
 272         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 273
 274         # This check is for users who have previously put 'android' in
 275         # the disk image filename to tell the config scripts to
 276         # prepare the kernel with android-specific boot options. That
 277         # behavior has been replaced with a more explicit option per
 278         # the error message below. The disk can have any name now and
 279         # doesn't need to include 'android' substring.
 280         if (mdesc.disks() and
 281                 os.path.split(mdesc.disks()[0])[-1].lower().count('android')):
 282             if 'android' not in mdesc.os_type():
 283                 fatal("It looks like you are trying to boot an Android " \
 284                       "platform.  To boot Android, you must specify " \
 285                       "--os-type with an appropriate Android release on " \
 286                       "the command line.")
 287
 288         # android-specific tweaks
 289         if 'android' in mdesc.os_type():
 290             # generic tweaks
 291             cmdline += " init=/init"
 292
 293             # release-specific tweaks
 294             if 'kitkat' in mdesc.os_type():
 295                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 296                            "android.bootanim=0 "
 297             elif 'nougat' in mdesc.os_type():
 298                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 299                            "android.bootanim=0 " + \
 300                            "vmalloc=640MB " + \
 301                            "android.early.fstab=/fstab.gem5 " + \
 302                            "androidboot.selinux=permissive " + \
 303                            "video=Virtual-1:1920x1080-16"
 304
 305         workload.command_line = fillInCmdline(mdesc, cmdline)
 306
 307         self.workload = workload
 308
 309         self.realview.setupBootLoader(self, binary, bootloader)
 310
 311     if external_memory:
 312         # I/O traffic enters iobus
 313         self.external_io = ExternalMaster(port_data="external_io",
 314                                           port_type=external_memory)
 315         self.external_io.port = self.iobus.slave
 316
 317         # Ensure iocache only receives traffic destined for (actual) memory.
 318         self.iocache = ExternalSlave(port_data="iocache",
 319                                      port_type=external_memory,
 320                                      addr_ranges=self.mem_ranges)
 321         self.iocache.port = self.iobus.master
 322
 323         # Let system_port get to nvmem and nothing else.
 324         self.bridge.ranges = [self.realview.nvmem.range]
 325
 326         self.realview.attachOnChipIO(self.iobus)
 327         # Attach off-chip devices
 328         self.realview.attachIO(self.iobus)
 329     elif ruby:
 330         self._dma_ports = [ ]
 331         self._mem_ports = [ ]
 332         self.realview.attachOnChipIO(self.iobus,
 333             dma_ports=self._dma_ports, mem_ports=self._mem_ports)
 334         self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
 335     else:
 336         self.realview.attachOnChipIO(self.membus, self.bridge)
 337         # Attach off-chip devices
 338         self.realview.attachIO(self.iobus)
 339
 340     for dev in pci_devices:
 341         self.realview.attachPciDevice(
 342             dev, self.iobus,
 343             dma_ports=self._dma_ports if ruby else None)
 344
 345     self.intrctrl = IntrControl()
 346     self.terminal = Terminal()
 347     self.vncserver = VncServer()
 348
 349     if vio_9p:
 350         attach_9p(self.realview, self.iobus)
 351
 352     if not ruby:
 353         self.system_port = self.membus.slave
 354
 355     if ruby:
 356         if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
 357             fatal("The MI_example protocol cannot implement Load/Store "
 358                   "Exclusive operations. Multicore ARM systems configured "
 359                   "with the MI_example protocol will not work properly.")
 360         warn("You are trying to use Ruby on ARM, which is not working "
 361              "properly yet.")
 362
 363     return self
 364
 365
 366 def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
 367     class BaseMalta(Malta):
 368         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 369         ide = IdeController(disks=Parent.disks,
 370                             pci_func=0, pci_dev=0, pci_bus=0)
 371
 372     self = System()
 373     if not mdesc:
 374         # generic system
 375         mdesc = SysConfig()
 376     self.readfile = mdesc.script()
 377     self.iobus = IOXBar()
 378     self.membus = MemBus()
 379     self.bridge = Bridge(delay='50ns')
 380     self.mem_ranges = [AddrRange('1GB')]
 381     self.bridge.master = self.iobus.slave
 382     self.bridge.slave = self.membus.master
 383     self.disks = makeCowDisks(mdesc.disks())
 384     self.malta = BaseMalta()
 385     self.malta.attachIO(self.iobus)
 386     self.malta.ide.pio = self.iobus.master
 387     self.malta.ide.dma = self.iobus.slave
 388     self.malta.ethernet.pio = self.iobus.master
 389     self.malta.ethernet.dma = self.iobus.slave
 390     self.simple_disk = SimpleDisk(disk=RawDiskImage(
 391         image_file = mdesc.disks()[0], read_only = True))
 392     self.intrctrl = IntrControl()
 393     self.mem_mode = mem_mode
 394     self.terminal = Terminal()
 395     self.console = binary('mips/console')
 396     if not cmdline:
 397         cmdline = 'root=/dev/hda1 console=ttyS0'
 398     self.workload = KernelWorkload(command_line=fillInCmdline(mdesc, cmdline))
 399
 400     self.system_port = self.membus.slave
 401
 402     return self
 403
 404 def x86IOAddress(port):
 405     IO_address_space_base = 0x8000000000000000
 406     return IO_address_space_base + port
 407
 408 def connectX86ClassicSystem(x86_sys, numCPUs):
 409     # Constants similar to x86_traits.hh
 410     IO_address_space_base = 0x8000000000000000
 411     pci_config_address_space_base = 0xc000000000000000
 412     interrupts_address_space_base = 0xa000000000000000
 413     APIC_range_size = 1 << 12;
 414
 415     x86_sys.membus = MemBus()
 416
 417     # North Bridge
 418     x86_sys.iobus = IOXBar()
 419     x86_sys.bridge = Bridge(delay='50ns')
 420     x86_sys.bridge.master = x86_sys.iobus.slave
 421     x86_sys.bridge.slave = x86_sys.membus.master
 422     # Allow the bridge to pass through:
 423     #  1) kernel configured PCI device memory map address: address range
 424     #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
 425     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
 426     #  3) everything in the IO address range up to the local APIC, and
 427     #  4) then the entire PCI address space and beyond.
 428     x86_sys.bridge.ranges = \
 429         [
 430         AddrRange(0xC0000000, 0xFFFF0000),
 431         AddrRange(IO_address_space_base,
 432                   interrupts_address_space_base - 1),
 433         AddrRange(pci_config_address_space_base,
 434                   Addr.max)
 435         ]
 436
 437     # Create a bridge from the IO bus to the memory bus to allow access to
 438     # the local APIC (two pages)
 439     x86_sys.apicbridge = Bridge(delay='50ns')
 440     x86_sys.apicbridge.slave = x86_sys.iobus.master
 441     x86_sys.apicbridge.master = x86_sys.membus.slave
 442     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 443                                            interrupts_address_space_base +
 444                                            numCPUs * APIC_range_size
 445                                            - 1)]
 446
 447     # connect the io bus
 448     x86_sys.pc.attachIO(x86_sys.iobus)
 449
 450     x86_sys.system_port = x86_sys.membus.slave
 451
 452 def connectX86RubySystem(x86_sys):
 453     # North Bridge
 454     x86_sys.iobus = IOXBar()
 455
 456     # add the ide to the list of dma devices that later need to attach to
 457     # dma controllers
 458     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 459     x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
 460
 461
 462 def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None, Ruby=False):
 463     self = System()
 464
 465     if workload is None:
 466         workload = X86FsWorkload()
 467     self.workload = workload
 468
 469     if not mdesc:
 470         # generic system
 471         mdesc = SysConfig()
 472     self.readfile = mdesc.script()
 473
 474     self.mem_mode = mem_mode
 475
 476     # Physical memory
 477     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
 478     # for various devices.  Hence, if the physical memory size is greater than
 479     # 3GB, we need to split it into two parts.
 480     excess_mem_size = \
 481         convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
 482     if excess_mem_size <= 0:
 483         self.mem_ranges = [AddrRange(mdesc.mem())]
 484     else:
 485         warn("Physical memory size specified is %s which is greater than " \
 486              "3GB.  Twice the number of memory controllers would be " \
 487              "created."  % (mdesc.mem()))
 488
 489         self.mem_ranges = [AddrRange('3GB'),
 490             AddrRange(Addr('4GB'), size = excess_mem_size)]
 491
 492     # Platform
 493     self.pc = Pc()
 494
 495     # Create and connect the busses required by each memory system
 496     if Ruby:
 497         connectX86RubySystem(self)
 498     else:
 499         connectX86ClassicSystem(self, numCPUs)
 500
 501     self.intrctrl = IntrControl()
 502
 503     # Disks
 504     disks = makeCowDisks(mdesc.disks())
 505     self.pc.south_bridge.ide.disks = disks
 506
 507     # Add in a Bios information structure.
 508     structures = [X86SMBiosBiosInformation()]
 509     workload.smbios_table.structures = structures
 510
 511     # Set up the Intel MP table
 512     base_entries = []
 513     ext_entries = []
 514     for i in range(numCPUs):
 515         bp = X86IntelMPProcessor(
 516                 local_apic_id = i,
 517                 local_apic_version = 0x14,
 518                 enable = True,
 519                 bootstrap = (i == 0))
 520         base_entries.append(bp)
 521     io_apic = X86IntelMPIOAPIC(
 522             id = numCPUs,
 523             version = 0x11,
 524             enable = True,
 525             address = 0xfec00000)
 526     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 527     base_entries.append(io_apic)
 528     # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 529     # but linux kernel cannot config PCI device if it was not connected to
 530     # PCI bus, so we fix PCI bus id to 0, and ISA bus id to 1.
 531     pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
 532     base_entries.append(pci_bus)
 533     isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
 534     base_entries.append(isa_bus)
 535     connect_busses = X86IntelMPBusHierarchy(bus_id=1,
 536             subtractive_decode=True, parent_bus=0)
 537     ext_entries.append(connect_busses)
 538     pci_dev4_inta = X86IntelMPIOIntAssignment(
 539             interrupt_type = 'INT',
 540             polarity = 'ConformPolarity',
 541             trigger = 'ConformTrigger',
 542             source_bus_id = 0,
 543             source_bus_irq = 0 + (4 << 2),
 544             dest_io_apic_id = io_apic.id,
 545             dest_io_apic_intin = 16)
 546     base_entries.append(pci_dev4_inta)
 547     def assignISAInt(irq, apicPin):
 548         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 549                 interrupt_type = 'ExtInt',
 550                 polarity = 'ConformPolarity',
 551                 trigger = 'ConformTrigger',
 552                 source_bus_id = 1,
 553                 source_bus_irq = irq,
 554                 dest_io_apic_id = io_apic.id,
 555                 dest_io_apic_intin = 0)
 556         base_entries.append(assign_8259_to_apic)
 557         assign_to_apic = X86IntelMPIOIntAssignment(
 558                 interrupt_type = 'INT',
 559                 polarity = 'ConformPolarity',
 560                 trigger = 'ConformTrigger',
 561                 source_bus_id = 1,
 562                 source_bus_irq = irq,
 563                 dest_io_apic_id = io_apic.id,
 564                 dest_io_apic_intin = apicPin)
 565         base_entries.append(assign_to_apic)
 566     assignISAInt(0, 2)
 567     assignISAInt(1, 1)
 568     for i in range(3, 15):
 569         assignISAInt(i, i)
 570     workload.intel_mp_table.base_entries = base_entries
 571     workload.intel_mp_table.ext_entries = ext_entries
 572
 573     return self
 574
 575 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
 576                        cmdline=None):
 577     # Build up the x86 system and then specialize it for Linux
 578     self = makeX86System(mem_mode, numCPUs, mdesc, X86FsLinux(), Ruby)
 579
 580     # We assume below that there's at least 1MB of memory. We'll require 2
 581     # just to avoid corner cases.
 582     phys_mem_size = sum([r.size() for r in self.mem_ranges])
 583     assert(phys_mem_size >= 0x200000)
 584     assert(len(self.mem_ranges) <= 2)
 585
 586     entries = \
 587        [
 588         # Mark the first megabyte of memory as reserved
 589         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 590         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 591         # Mark the rest of physical memory as available
 592         X86E820Entry(addr = 0x100000,
 593                 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
 594                 range_type = 1),
 595         ]
 596
 597     # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
 598     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
 599     # specific range can pass though bridge to iobus.
 600     if len(self.mem_ranges) == 1:
 601         entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
 602             size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
 603             range_type=2))
 604
 605     # Reserve the last 16kB of the 32-bit address space for the m5op interface
 606     entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
 607
 608     # In case the physical memory is greater than 3GB, we split it into two
 609     # parts and add a separate e820 entry for the second part.  This entry
 610     # starts at 0x100000000,  which is the first address after the space
 611     # reserved for devices.
 612     if len(self.mem_ranges) == 2:
 613         entries.append(X86E820Entry(addr = 0x100000000,
 614             size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
 615
 616     self.workload.e820_table.entries = entries
 617
 618     # Command line
 619     if not cmdline:
 620         cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
 621     self.workload.command_line = fillInCmdline(mdesc, cmdline)
 622     return self
 623
 624 def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
 625     self = System()
 626     if not mdesc:
 627         # generic system
 628         mdesc = SysConfig()
 629     self.mem_mode = mem_mode
 630     self.mem_ranges = [AddrRange(mdesc.mem())]
 631
 632     self.workload = RiscvBareMetal()
 633
 634     self.iobus = IOXBar()
 635     self.membus = MemBus()
 636
 637     self.bridge = Bridge(delay='50ns')
 638     self.bridge.master = self.iobus.slave
 639     self.bridge.slave = self.membus.master
 640     # Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO space
 641     IO_address_space_base = 0x00FF000000000000
 642     self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
 643
 644     self.system_port = self.membus.slave
 645     return self
 646
 647 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 648     self = Root(full_system = full_system)
 649     self.testsys = testSystem
 650     self.drivesys = driveSystem
 651     self.etherlink = EtherLink()
 652
 653     if hasattr(testSystem, 'realview'):
 654         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 655         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 656     elif hasattr(testSystem, 'tsunami'):
 657         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 658         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 659     else:
 660         fatal("Don't know how to connect these system together")
 661
 662     if dumpfile:
 663         self.etherdump = EtherDump(file=dumpfile)
 664         self.etherlink.dump = Parent.etherdump
 665
 666     return self
 667
 668
 669 def makeDistRoot(testSystem,
 670                  rank,
 671                  size,
 672                  server_name,
 673                  server_port,
 674                  sync_repeat,
 675                  sync_start,
 676                  linkspeed,
 677                  linkdelay,
 678                  dumpfile):
 679     self = Root(full_system = True)
 680     self.testsys = testSystem
 681
 682     self.etherlink = DistEtherLink(speed = linkspeed,
 683                                    delay = linkdelay,
 684                                    dist_rank = rank,
 685                                    dist_size = size,
 686                                    server_name = server_name,
 687                                    server_port = server_port,
 688                                    sync_start = sync_start,
 689                                    sync_repeat = sync_repeat)
 690
 691     if hasattr(testSystem, 'realview'):
 692         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 693     elif hasattr(testSystem, 'tsunami'):
 694         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 695     else:
 696         fatal("Don't know how to connect DistEtherLink to this system")
 697
 698     if dumpfile:
 699         self.etherdump = EtherDump(file=dumpfile)
 700         self.etherlink.dump = Parent.etherdump
 701
 702     return self