1 # Copyright (c) 2010-2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 from m5
.objects
import *
43 from Benchmarks
import *
46 class CowIdeDisk(IdeDisk
):
47 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
50 def childImage(self
, ci
):
51 self
.image
.child
.image_file
= ci
53 class MemBus(CoherentXBar
):
54 badaddr_responder
= BadAddr()
55 default
= Self
.badaddr_responder
.pio
58 def makeLinuxAlphaSystem(mem_mode
, mdesc
= None, ruby
= False):
60 class BaseTsunami(Tsunami
):
61 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
62 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
63 pci_func
=0, pci_dev
=0, pci_bus
=0)
65 self
= LinuxAlphaSystem()
69 self
.readfile
= mdesc
.script()
71 self
.tsunami
= BaseTsunami()
73 # Create the io bus to connect all device ports
74 self
.iobus
= NoncoherentXBar()
75 self
.tsunami
.attachIO(self
.iobus
)
77 self
.tsunami
.ide
.pio
= self
.iobus
.master
78 self
.tsunami
.ide
.config
= self
.iobus
.master
80 self
.tsunami
.ethernet
.pio
= self
.iobus
.master
81 self
.tsunami
.ethernet
.config
= self
.iobus
.master
84 # Store the dma devices for later connection to dma ruby ports.
85 # Append an underscore to dma_ports to avoid the SimObjectVector check.
86 self
._dma
_ports
= [self
.tsunami
.ide
.dma
, self
.tsunami
.ethernet
.dma
]
88 self
.membus
= MemBus()
90 # By default the bridge responds to all addresses above the I/O
91 # base address (including the PCI config space)
92 IO_address_space_base
= 0x80000000000
93 self
.bridge
= Bridge(delay
='50ns',
94 ranges
= [AddrRange(IO_address_space_base
, Addr
.max)])
95 self
.bridge
.master
= self
.iobus
.slave
96 self
.bridge
.slave
= self
.membus
.master
98 self
.tsunami
.ide
.dma
= self
.iobus
.slave
99 self
.tsunami
.ethernet
.dma
= self
.iobus
.slave
101 self
.system_port
= self
.membus
.slave
103 self
.mem_ranges
= [AddrRange(mdesc
.mem())]
104 self
.disk0
= CowIdeDisk(driveID
='master')
105 self
.disk2
= CowIdeDisk(driveID
='master')
106 self
.disk0
.childImage(mdesc
.disk())
107 self
.disk2
.childImage(disk('linux-bigswap2.img'))
108 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
110 self
.intrctrl
= IntrControl()
111 self
.mem_mode
= mem_mode
112 self
.terminal
= Terminal()
113 self
.kernel
= binary('vmlinux')
114 self
.pal
= binary('ts_osfpal')
115 self
.console
= binary('console')
116 self
.boot_osflags
= 'root=/dev/hda1 console=ttyS0'
120 def makeSparcSystem(mem_mode
, mdesc
= None):
121 # Constants from iob.cc and uart8250.cc
122 iob_man_addr
= 0x9800000000
125 class CowMmDisk(MmDisk
):
126 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
129 def childImage(self
, ci
):
130 self
.image
.child
.image_file
= ci
136 self
.readfile
= mdesc
.script()
137 self
.iobus
= NoncoherentXBar()
138 self
.membus
= MemBus()
139 self
.bridge
= Bridge(delay
='50ns')
141 self
.t1000
.attachOnChipIO(self
.membus
)
142 self
.t1000
.attachIO(self
.iobus
)
143 self
.mem_ranges
= [AddrRange(Addr('1MB'), size
= '64MB'),
144 AddrRange(Addr('2GB'), size
='256MB')]
145 self
.bridge
.master
= self
.iobus
.slave
146 self
.bridge
.slave
= self
.membus
.master
147 self
.rom
.port
= self
.membus
.master
148 self
.nvram
.port
= self
.membus
.master
149 self
.hypervisor_desc
.port
= self
.membus
.master
150 self
.partition_desc
.port
= self
.membus
.master
151 self
.intrctrl
= IntrControl()
152 self
.disk0
= CowMmDisk()
153 self
.disk0
.childImage(disk('disk.s10hw2'))
154 self
.disk0
.pio
= self
.iobus
.master
156 # The puart0 and hvuart are placed on the IO bus, so create ranges
157 # for them. The remaining IO range is rather fragmented, so poke
158 # holes for the iob and partition descriptors etc.
159 self
.bridge
.ranges
= \
161 AddrRange(self
.t1000
.puart0
.pio_addr
,
162 self
.t1000
.puart0
.pio_addr
+ uart_pio_size
- 1),
163 AddrRange(self
.disk0
.pio_addr
,
164 self
.t1000
.fake_jbi
.pio_addr
+
165 self
.t1000
.fake_jbi
.pio_size
- 1),
166 AddrRange(self
.t1000
.fake_clk
.pio_addr
,
168 AddrRange(self
.t1000
.fake_l2_1
.pio_addr
,
169 self
.t1000
.fake_ssi
.pio_addr
+
170 self
.t1000
.fake_ssi
.pio_size
- 1),
171 AddrRange(self
.t1000
.hvuart
.pio_addr
,
172 self
.t1000
.hvuart
.pio_addr
+ uart_pio_size
- 1)
174 self
.reset_bin
= binary('reset_new.bin')
175 self
.hypervisor_bin
= binary('q_new.bin')
176 self
.openboot_bin
= binary('openboot_new.bin')
177 self
.nvram_bin
= binary('nvram1')
178 self
.hypervisor_desc_bin
= binary('1up-hv.bin')
179 self
.partition_desc_bin
= binary('1up-md.bin')
181 self
.system_port
= self
.membus
.slave
185 def makeArmSystem(mem_mode
, machine_type
, mdesc
= None,
186 dtb_filename
= None, bare_metal
=False):
192 self
= LinuxArmSystem()
198 self
.readfile
= mdesc
.script()
199 self
.iobus
= NoncoherentXBar()
200 self
.membus
= MemBus()
201 self
.membus
.badaddr_responder
.warn_access
= "warn"
202 self
.bridge
= Bridge(delay
='50ns')
203 self
.bridge
.master
= self
.iobus
.slave
204 self
.bridge
.slave
= self
.membus
.master
206 self
.mem_mode
= mem_mode
208 if machine_type
== "RealView_PBX":
209 self
.realview
= RealViewPBX()
210 elif machine_type
== "RealView_EB":
211 self
.realview
= RealViewEB()
212 elif machine_type
== "VExpress_ELT":
213 self
.realview
= VExpress_ELT()
214 elif machine_type
== "VExpress_EMM":
215 self
.realview
= VExpress_EMM()
216 elif machine_type
== "VExpress_EMM64":
217 self
.realview
= VExpress_EMM64()
219 print "Unknown Machine Type"
222 self
.cf0
= CowIdeDisk(driveID
='master')
223 self
.cf0
.childImage(mdesc
.disk())
225 # Attach any PCI devices this platform supports
226 self
.realview
.attachPciDevices()
227 # default to an IDE controller rather than a CF one
229 self
.realview
.ide
.disks
= [self
.cf0
]
231 self
.realview
.cf_ctrl
.disks
= [self
.cf0
]
234 # EOT character on UART will end the simulation
235 self
.realview
.uart
.end_on_eot
= True
236 self
.mem_ranges
= [AddrRange(self
.realview
.mem_start_addr
,
239 if machine_type
== "VExpress_EMM64":
240 self
.kernel
= binary('vmlinux-3.16-aarch64-vexpress-emm64-pcie')
241 elif machine_type
== "VExpress_EMM":
242 self
.kernel
= binary('vmlinux-3.3-arm-vexpress-emm-pcie')
244 self
.kernel
= binary('vmlinux.arm.smp.fb.2.6.38.8')
247 self
.dtb_filename
= binary(dtb_filename
)
248 self
.machine_type
= machine_type
249 # Ensure that writes to the UART actually go out early in the boot
250 boot_flags
= 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
251 'lpj=19988480 norandmaps rw loglevel=8 ' + \
252 'mem=%s root=/dev/sda1' % mdesc
.mem()
255 size_remain
= long(Addr(mdesc
.mem()))
256 for region
in self
.realview
._mem
_regions
:
257 if size_remain
> long(region
[1]):
258 self
.mem_ranges
.append(AddrRange(region
[0], size
=region
[1]))
259 size_remain
= size_remain
- long(region
[1])
261 self
.mem_ranges
.append(AddrRange(region
[0], size
=size_remain
))
264 warn("Memory size specified spans more than one region. Creating" \
265 " another memory controller for that range.")
268 fatal("The currently selected ARM platforms doesn't support" \
269 " the amount of DRAM you've selected. Please try" \
273 self
.realview
.setupBootLoader(self
.membus
, self
, binary
)
274 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
275 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
277 if mdesc
.disk().lower().count('android'):
278 boot_flags
+= " init=/init "
279 self
.boot_osflags
= boot_flags
280 self
.realview
.attachOnChipIO(self
.membus
, self
.bridge
)
281 self
.realview
.attachIO(self
.iobus
)
282 self
.intrctrl
= IntrControl()
283 self
.terminal
= Terminal()
284 self
.vncserver
= VncServer()
286 self
.system_port
= self
.membus
.slave
291 def makeLinuxMipsSystem(mem_mode
, mdesc
= None):
292 class BaseMalta(Malta
):
293 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
294 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
295 pci_func
=0, pci_dev
=0, pci_bus
=0)
297 self
= LinuxMipsSystem()
301 self
.readfile
= mdesc
.script()
302 self
.iobus
= NoncoherentXBar()
303 self
.membus
= MemBus()
304 self
.bridge
= Bridge(delay
='50ns')
305 self
.mem_ranges
= [AddrRange('1GB')]
306 self
.bridge
.master
= self
.iobus
.slave
307 self
.bridge
.slave
= self
.membus
.master
308 self
.disk0
= CowIdeDisk(driveID
='master')
309 self
.disk2
= CowIdeDisk(driveID
='master')
310 self
.disk0
.childImage(mdesc
.disk())
311 self
.disk2
.childImage(disk('linux-bigswap2.img'))
312 self
.malta
= BaseMalta()
313 self
.malta
.attachIO(self
.iobus
)
314 self
.malta
.ide
.pio
= self
.iobus
.master
315 self
.malta
.ide
.config
= self
.iobus
.master
316 self
.malta
.ide
.dma
= self
.iobus
.slave
317 self
.malta
.ethernet
.pio
= self
.iobus
.master
318 self
.malta
.ethernet
.config
= self
.iobus
.master
319 self
.malta
.ethernet
.dma
= self
.iobus
.slave
320 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
322 self
.intrctrl
= IntrControl()
323 self
.mem_mode
= mem_mode
324 self
.terminal
= Terminal()
325 self
.kernel
= binary('mips/vmlinux')
326 self
.console
= binary('mips/console')
327 self
.boot_osflags
= 'root=/dev/hda1 console=ttyS0'
329 self
.system_port
= self
.membus
.slave
333 def x86IOAddress(port
):
334 IO_address_space_base
= 0x8000000000000000
335 return IO_address_space_base
+ port
337 def connectX86ClassicSystem(x86_sys
, numCPUs
):
338 # Constants similar to x86_traits.hh
339 IO_address_space_base
= 0x8000000000000000
340 pci_config_address_space_base
= 0xc000000000000000
341 interrupts_address_space_base
= 0xa000000000000000
342 APIC_range_size
= 1 << 12;
344 x86_sys
.membus
= MemBus()
347 x86_sys
.iobus
= NoncoherentXBar()
348 x86_sys
.bridge
= Bridge(delay
='50ns')
349 x86_sys
.bridge
.master
= x86_sys
.iobus
.slave
350 x86_sys
.bridge
.slave
= x86_sys
.membus
.master
351 # Allow the bridge to pass through:
352 # 1) kernel configured PCI device memory map address: address range
353 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
354 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
355 # 3) everything in the IO address range up to the local APIC, and
356 # 4) then the entire PCI address space and beyond.
357 x86_sys
.bridge
.ranges
= \
359 AddrRange(0xC0000000, 0xFFFF0000),
360 AddrRange(IO_address_space_base
,
361 interrupts_address_space_base
- 1),
362 AddrRange(pci_config_address_space_base
,
366 # Create a bridge from the IO bus to the memory bus to allow access to
367 # the local APIC (two pages)
368 x86_sys
.apicbridge
= Bridge(delay
='50ns')
369 x86_sys
.apicbridge
.slave
= x86_sys
.iobus
.master
370 x86_sys
.apicbridge
.master
= x86_sys
.membus
.slave
371 x86_sys
.apicbridge
.ranges
= [AddrRange(interrupts_address_space_base
,
372 interrupts_address_space_base
+
373 numCPUs
* APIC_range_size
377 x86_sys
.pc
.attachIO(x86_sys
.iobus
)
379 x86_sys
.system_port
= x86_sys
.membus
.slave
381 def connectX86RubySystem(x86_sys
):
383 x86_sys
.iobus
= NoncoherentXBar()
385 # add the ide to the list of dma devices that later need to attach to
387 x86_sys
._dma
_ports
= [x86_sys
.pc
.south_bridge
.ide
.dma
]
388 x86_sys
.pc
.attachIO(x86_sys
.iobus
, x86_sys
._dma
_ports
)
391 def makeX86System(mem_mode
, numCPUs
= 1, mdesc
= None, self
= None,
399 self
.readfile
= mdesc
.script()
401 self
.mem_mode
= mem_mode
404 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
405 # for various devices. Hence, if the physical memory size is greater than
406 # 3GB, we need to split it into two parts.
408 convert
.toMemorySize(mdesc
.mem()) - convert
.toMemorySize('3GB')
409 if excess_mem_size
<= 0:
410 self
.mem_ranges
= [AddrRange(mdesc
.mem())]
412 warn("Physical memory size specified is %s which is greater than " \
413 "3GB. Twice the number of memory controllers would be " \
414 "created." % (mdesc
.mem()))
416 self
.mem_ranges
= [AddrRange('3GB'),
417 AddrRange(Addr('4GB'), size
= excess_mem_size
)]
422 # Create and connect the busses required by each memory system
424 connectX86RubySystem(self
)
426 connectX86ClassicSystem(self
, numCPUs
)
428 self
.intrctrl
= IntrControl()
431 disk0
= CowIdeDisk(driveID
='master')
432 disk2
= CowIdeDisk(driveID
='master')
433 disk0
.childImage(mdesc
.disk())
434 disk2
.childImage(disk('linux-bigswap2.img'))
435 self
.pc
.south_bridge
.ide
.disks
= [disk0
, disk2
]
437 # Add in a Bios information structure.
438 structures
= [X86SMBiosBiosInformation()]
439 self
.smbios_table
.structures
= structures
441 # Set up the Intel MP table
444 for i
in xrange(numCPUs
):
445 bp
= X86IntelMPProcessor(
447 local_apic_version
= 0x14,
449 bootstrap
= (i
== 0))
450 base_entries
.append(bp
)
451 io_apic
= X86IntelMPIOAPIC(
455 address
= 0xfec00000)
456 self
.pc
.south_bridge
.io_apic
.apic_id
= io_apic
.id
457 base_entries
.append(io_apic
)
458 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
459 # but linux kernel cannot config PCI device if it was not connected to PCI bus,
460 # so we fix PCI bus id to 0, and ISA bus id to 1.
461 pci_bus
= X86IntelMPBus(bus_id
= 0, bus_type
='PCI')
462 base_entries
.append(pci_bus
)
463 isa_bus
= X86IntelMPBus(bus_id
= 1, bus_type
='ISA')
464 base_entries
.append(isa_bus
)
465 connect_busses
= X86IntelMPBusHierarchy(bus_id
=1,
466 subtractive_decode
=True, parent_bus
=0)
467 ext_entries
.append(connect_busses
)
468 pci_dev4_inta
= X86IntelMPIOIntAssignment(
469 interrupt_type
= 'INT',
470 polarity
= 'ConformPolarity',
471 trigger
= 'ConformTrigger',
473 source_bus_irq
= 0 + (4 << 2),
474 dest_io_apic_id
= io_apic
.id,
475 dest_io_apic_intin
= 16)
476 base_entries
.append(pci_dev4_inta
)
477 def assignISAInt(irq
, apicPin
):
478 assign_8259_to_apic
= X86IntelMPIOIntAssignment(
479 interrupt_type
= 'ExtInt',
480 polarity
= 'ConformPolarity',
481 trigger
= 'ConformTrigger',
483 source_bus_irq
= irq
,
484 dest_io_apic_id
= io_apic
.id,
485 dest_io_apic_intin
= 0)
486 base_entries
.append(assign_8259_to_apic
)
487 assign_to_apic
= X86IntelMPIOIntAssignment(
488 interrupt_type
= 'INT',
489 polarity
= 'ConformPolarity',
490 trigger
= 'ConformTrigger',
492 source_bus_irq
= irq
,
493 dest_io_apic_id
= io_apic
.id,
494 dest_io_apic_intin
= apicPin
)
495 base_entries
.append(assign_to_apic
)
498 for i
in range(3, 15):
500 self
.intel_mp_table
.base_entries
= base_entries
501 self
.intel_mp_table
.ext_entries
= ext_entries
503 def makeLinuxX86System(mem_mode
, numCPUs
= 1, mdesc
= None,
505 self
= LinuxX86System()
507 # Build up the x86 system and then specialize it for Linux
508 makeX86System(mem_mode
, numCPUs
, mdesc
, self
, Ruby
)
510 # We assume below that there's at least 1MB of memory. We'll require 2
511 # just to avoid corner cases.
512 phys_mem_size
= sum(map(lambda r
: r
.size(), self
.mem_ranges
))
513 assert(phys_mem_size
>= 0x200000)
514 assert(len(self
.mem_ranges
) <= 2)
518 # Mark the first megabyte of memory as reserved
519 X86E820Entry(addr
= 0, size
= '639kB', range_type
= 1),
520 X86E820Entry(addr
= 0x9fc00, size
= '385kB', range_type
= 2),
521 # Mark the rest of physical memory as available
522 X86E820Entry(addr
= 0x100000,
523 size
= '%dB' % (self
.mem_ranges
[0].size() - 0x100000),
527 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
528 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
529 # specific range can pass though bridge to iobus.
530 if len(self
.mem_ranges
) == 1:
531 entries
.append(X86E820Entry(addr
= self
.mem_ranges
[0].size(),
532 size
='%dB' % (0xC0000000 - self
.mem_ranges
[0].size()),
535 # Reserve the last 16kB of the 32-bit address space for the m5op interface
536 entries
.append(X86E820Entry(addr
=0xFFFF0000, size
='64kB', range_type
=2))
538 # In case the physical memory is greater than 3GB, we split it into two
539 # parts and add a separate e820 entry for the second part. This entry
540 # starts at 0x100000000, which is the first address after the space
541 # reserved for devices.
542 if len(self
.mem_ranges
) == 2:
543 entries
.append(X86E820Entry(addr
= 0x100000000,
544 size
= '%dB' % (self
.mem_ranges
[1].size()), range_type
= 1))
546 self
.e820_table
.entries
= entries
549 self
.boot_osflags
= 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
551 self
.kernel
= binary('x86_64-vmlinux-2.6.22.9')
555 def makeDualRoot(full_system
, testSystem
, driveSystem
, dumpfile
):
556 self
= Root(full_system
= full_system
)
557 self
.testsys
= testSystem
558 self
.drivesys
= driveSystem
559 self
.etherlink
= EtherLink()
561 if hasattr(testSystem
, 'realview'):
562 self
.etherlink
.int0
= Parent
.testsys
.realview
.ethernet
.interface
563 self
.etherlink
.int1
= Parent
.drivesys
.realview
.ethernet
.interface
564 elif hasattr(testSystem
, 'tsunami'):
565 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
566 self
.etherlink
.int1
= Parent
.drivesys
.tsunami
.ethernet
.interface
568 fatal("Don't know how to connect these system together")
571 self
.etherdump
= EtherDump(file=dumpfile
)
572 self
.etherlink
.dump
= Parent
.etherdump