1 # Copyright (c) 2010-2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 from m5
.objects
import *
43 from Benchmarks
import *
44 from m5
.util
import convert
46 class CowIdeDisk(IdeDisk
):
47 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
50 def childImage(self
, ci
):
51 self
.image
.child
.image_file
= ci
54 badaddr_responder
= BadAddr()
55 default
= Self
.badaddr_responder
.pio
58 def makeLinuxAlphaSystem(mem_mode
, mdesc
= None):
59 IO_address_space_base
= 0x80000000000
60 class BaseTsunami(Tsunami
):
61 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
62 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
63 pci_func
=0, pci_dev
=0, pci_bus
=0)
65 self
= LinuxAlphaSystem()
69 self
.readfile
= mdesc
.script()
70 self
.iobus
= Bus(bus_id
=0)
71 self
.membus
= MemBus(bus_id
=1)
72 # By default the bridge responds to all addresses above the I/O
73 # base address (including the PCI config space)
74 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns',
75 ranges
= [AddrRange(IO_address_space_base
, Addr
.max)])
76 self
.physmem
= PhysicalMemory(range = AddrRange(mdesc
.mem()))
77 self
.bridge
.master
= self
.iobus
.slave
78 self
.bridge
.slave
= self
.membus
.master
79 self
.physmem
.port
= self
.membus
.master
80 self
.disk0
= CowIdeDisk(driveID
='master')
81 self
.disk2
= CowIdeDisk(driveID
='master')
82 self
.disk0
.childImage(mdesc
.disk())
83 self
.disk2
.childImage(disk('linux-bigswap2.img'))
84 self
.tsunami
= BaseTsunami()
85 self
.tsunami
.attachIO(self
.iobus
)
86 self
.tsunami
.ide
.pio
= self
.iobus
.master
87 self
.tsunami
.ide
.config
= self
.iobus
.master
88 self
.tsunami
.ide
.dma
= self
.iobus
.slave
89 self
.tsunami
.ethernet
.pio
= self
.iobus
.master
90 self
.tsunami
.ethernet
.config
= self
.iobus
.master
91 self
.tsunami
.ethernet
.dma
= self
.iobus
.slave
92 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
94 self
.intrctrl
= IntrControl()
95 self
.mem_mode
= mem_mode
96 self
.terminal
= Terminal()
97 self
.kernel
= binary('vmlinux')
98 self
.pal
= binary('ts_osfpal')
99 self
.console
= binary('console')
100 self
.boot_osflags
= 'root=/dev/hda1 console=ttyS0'
102 self
.system_port
= self
.membus
.slave
106 def makeLinuxAlphaRubySystem(mem_mode
, mdesc
= None):
107 class BaseTsunami(Tsunami
):
108 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
109 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
110 pci_func
=0, pci_dev
=0, pci_bus
=0)
112 physmem
= PhysicalMemory(range = AddrRange(mdesc
.mem()))
113 self
= LinuxAlphaSystem(physmem
= physmem
)
117 self
.readfile
= mdesc
.script()
119 # Create pio bus to connect all device pio ports to rubymem's pio port
120 self
.piobus
= Bus(bus_id
=0)
123 # Pio functional accesses from devices need direct access to memory
124 # RubyPort currently does support functional accesses. Therefore provide
125 # the piobus a direct connection to physical memory
127 self
.piobus
.master_port
= physmem
.port
129 self
.disk0
= CowIdeDisk(driveID
='master')
130 self
.disk2
= CowIdeDisk(driveID
='master')
131 self
.disk0
.childImage(mdesc
.disk())
132 self
.disk2
.childImage(disk('linux-bigswap2.img'))
133 self
.tsunami
= BaseTsunami()
134 self
.tsunami
.attachIO(self
.piobus
)
135 self
.tsunami
.ide
.pio
= self
.piobus
.master
136 self
.tsunami
.ide
.config
= self
.piobus
.master
137 self
.tsunami
.ide
.dma
= self
.piobus
.slave
138 self
.tsunami
.ethernet
.pio
= self
.piobus
.master
139 self
.tsunami
.ethernet
.config
= self
.piobus
.master
140 self
.tsunami
.ethernet
.dma
= self
.piobus
.slave
143 # Store the dma devices for later connection to dma ruby ports.
144 # Append an underscore to dma_devices to avoid the SimObjectVector check.
146 self
._dma
_devices
= [self
.tsunami
.ide
, self
.tsunami
.ethernet
]
148 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
150 self
.intrctrl
= IntrControl()
151 self
.mem_mode
= mem_mode
152 self
.terminal
= Terminal()
153 self
.kernel
= binary('vmlinux')
154 self
.pal
= binary('ts_osfpal')
155 self
.console
= binary('console')
156 self
.boot_osflags
= 'root=/dev/hda1 console=ttyS0'
160 def makeSparcSystem(mem_mode
, mdesc
= None):
161 # Constants from iob.cc and uart8250.cc
162 iob_man_addr
= 0x9800000000
165 class CowMmDisk(MmDisk
):
166 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
169 def childImage(self
, ci
):
170 self
.image
.child
.image_file
= ci
176 self
.readfile
= mdesc
.script()
177 self
.iobus
= Bus(bus_id
=0)
178 self
.membus
= MemBus(bus_id
=1)
179 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
181 self
.t1000
.attachOnChipIO(self
.membus
)
182 self
.t1000
.attachIO(self
.iobus
)
183 self
.physmem
= PhysicalMemory(range = AddrRange(Addr('1MB'), size
= '64MB'), zero
= True)
184 self
.physmem2
= PhysicalMemory(range = AddrRange(Addr('2GB'), size
='256MB'), zero
= True)
185 self
.bridge
.master
= self
.iobus
.slave
186 self
.bridge
.slave
= self
.membus
.master
187 self
.physmem
.port
= self
.membus
.master
188 self
.physmem2
.port
= self
.membus
.master
189 self
.rom
.port
= self
.membus
.master
190 self
.nvram
.port
= self
.membus
.master
191 self
.hypervisor_desc
.port
= self
.membus
.master
192 self
.partition_desc
.port
= self
.membus
.master
193 self
.intrctrl
= IntrControl()
194 self
.disk0
= CowMmDisk()
195 self
.disk0
.childImage(disk('disk.s10hw2'))
196 self
.disk0
.pio
= self
.iobus
.master
198 # The puart0 and hvuart are placed on the IO bus, so create ranges
199 # for them. The remaining IO range is rather fragmented, so poke
200 # holes for the iob and partition descriptors etc.
201 self
.bridge
.ranges
= \
203 AddrRange(self
.t1000
.puart0
.pio_addr
,
204 self
.t1000
.puart0
.pio_addr
+ uart_pio_size
- 1),
205 AddrRange(self
.disk0
.pio_addr
,
206 self
.t1000
.fake_jbi
.pio_addr
+
207 self
.t1000
.fake_jbi
.pio_size
- 1),
208 AddrRange(self
.t1000
.fake_clk
.pio_addr
,
210 AddrRange(self
.t1000
.fake_l2_1
.pio_addr
,
211 self
.t1000
.fake_ssi
.pio_addr
+
212 self
.t1000
.fake_ssi
.pio_size
- 1),
213 AddrRange(self
.t1000
.hvuart
.pio_addr
,
214 self
.t1000
.hvuart
.pio_addr
+ uart_pio_size
- 1)
216 self
.reset_bin
= binary('reset_new.bin')
217 self
.hypervisor_bin
= binary('q_new.bin')
218 self
.openboot_bin
= binary('openboot_new.bin')
219 self
.nvram_bin
= binary('nvram1')
220 self
.hypervisor_desc_bin
= binary('1up-hv.bin')
221 self
.partition_desc_bin
= binary('1up-md.bin')
223 self
.system_port
= self
.membus
.slave
227 def makeArmSystem(mem_mode
, machine_type
, mdesc
= None, bare_metal
=False):
233 self
= LinuxArmSystem()
239 self
.readfile
= mdesc
.script()
240 self
.iobus
= Bus(bus_id
=0)
241 self
.membus
= MemBus(bus_id
=1)
242 self
.membus
.badaddr_responder
.warn_access
= "warn"
243 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
244 self
.bridge
.master
= self
.iobus
.slave
245 self
.bridge
.slave
= self
.membus
.master
247 self
.mem_mode
= mem_mode
249 if machine_type
== "RealView_PBX":
250 self
.realview
= RealViewPBX()
251 elif machine_type
== "RealView_EB":
252 self
.realview
= RealViewEB()
253 elif machine_type
== "VExpress_ELT":
254 self
.realview
= VExpress_ELT()
256 print "Unknown Machine Type"
259 self
.cf0
= CowIdeDisk(driveID
='master')
260 self
.cf0
.childImage(mdesc
.disk())
261 # default to an IDE controller rather than a CF one
262 # assuming we've got one
264 self
.realview
.ide
.disks
= [self
.cf0
]
266 self
.realview
.cf_ctrl
.disks
= [self
.cf0
]
269 # EOT character on UART will end the simulation
270 self
.realview
.uart
.end_on_eot
= True
271 self
.physmem
= PhysicalMemory(range = AddrRange(Addr(mdesc
.mem())),
274 self
.kernel
= binary('vmlinux.arm.smp.fb.2.6.38.8')
275 self
.machine_type
= machine_type
276 if convert
.toMemorySize(mdesc
.mem()) > convert
.toMemorySize('256MB'):
277 print "The currently implemented ARM platforms only easily support 256MB of DRAM"
278 print "It might be possible to get some more by using 256MB@0x30000000, but this"
279 print "is untested and may require some heroics"
281 boot_flags
= 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
282 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc
.mem()
284 self
.physmem
= PhysicalMemory(range = AddrRange(Addr(mdesc
.mem())),
286 self
.nvmem
= PhysicalMemory(range = AddrRange(Addr('2GB'),
287 size
= '64MB'), zero
= True)
288 self
.nvmem
.port
= self
.membus
.master
289 self
.boot_loader
= binary('boot.arm')
290 self
.boot_loader_mem
= self
.nvmem
291 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
292 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
294 if mdesc
.disk().lower().count('android'):
295 boot_flags
+= " init=/init "
296 self
.boot_osflags
= boot_flags
298 self
.physmem
.port
= self
.membus
.master
299 self
.realview
.attachOnChipIO(self
.membus
, self
.bridge
)
300 self
.realview
.attachIO(self
.iobus
)
301 self
.intrctrl
= IntrControl()
302 self
.terminal
= Terminal()
303 self
.vncserver
= VncServer()
305 self
.system_port
= self
.membus
.slave
310 def makeLinuxMipsSystem(mem_mode
, mdesc
= None):
311 class BaseMalta(Malta
):
312 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
313 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
314 pci_func
=0, pci_dev
=0, pci_bus
=0)
316 self
= LinuxMipsSystem()
320 self
.readfile
= mdesc
.script()
321 self
.iobus
= Bus(bus_id
=0)
322 self
.membus
= MemBus(bus_id
=1)
323 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
324 self
.physmem
= PhysicalMemory(range = AddrRange('1GB'))
325 self
.bridge
.master
= self
.iobus
.slave
326 self
.bridge
.slave
= self
.membus
.master
327 self
.physmem
.port
= self
.membus
.master
328 self
.disk0
= CowIdeDisk(driveID
='master')
329 self
.disk2
= CowIdeDisk(driveID
='master')
330 self
.disk0
.childImage(mdesc
.disk())
331 self
.disk2
.childImage(disk('linux-bigswap2.img'))
332 self
.malta
= BaseMalta()
333 self
.malta
.attachIO(self
.iobus
)
334 self
.malta
.ide
.pio
= self
.iobus
.master
335 self
.malta
.ide
.config
= self
.iobus
.master
336 self
.malta
.ide
.dma
= self
.iobus
.slave
337 self
.malta
.ethernet
.pio
= self
.iobus
.master
338 self
.malta
.ethernet
.config
= self
.iobus
.master
339 self
.malta
.ethernet
.dma
= self
.iobus
.slave
340 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
342 self
.intrctrl
= IntrControl()
343 self
.mem_mode
= mem_mode
344 self
.terminal
= Terminal()
345 self
.kernel
= binary('mips/vmlinux')
346 self
.console
= binary('mips/console')
347 self
.boot_osflags
= 'root=/dev/hda1 console=ttyS0'
349 self
.system_port
= self
.membus
.slave
353 def x86IOAddress(port
):
354 IO_address_space_base
= 0x8000000000000000
355 return IO_address_space_base
+ port
357 def connectX86ClassicSystem(x86_sys
, numCPUs
):
358 # Constants similar to x86_traits.hh
359 IO_address_space_base
= 0x8000000000000000
360 pci_config_address_space_base
= 0xc000000000000000
361 interrupts_address_space_base
= 0xa000000000000000
362 APIC_range_size
= 1 << 12;
364 x86_sys
.membus
= MemBus(bus_id
=1)
365 x86_sys
.physmem
.port
= x86_sys
.membus
.master
368 x86_sys
.iobus
= Bus(bus_id
=0)
369 x86_sys
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
370 x86_sys
.bridge
.master
= x86_sys
.iobus
.slave
371 x86_sys
.bridge
.slave
= x86_sys
.membus
.master
372 # Allow the bridge to pass through the IO APIC (two pages),
373 # everything in the IO address range up to the local APIC, and
374 # then the entire PCI address space and beyond
375 x86_sys
.bridge
.ranges
= \
377 AddrRange(x86_sys
.pc
.south_bridge
.io_apic
.pio_addr
,
378 x86_sys
.pc
.south_bridge
.io_apic
.pio_addr
+
379 APIC_range_size
- 1),
380 AddrRange(IO_address_space_base
,
381 interrupts_address_space_base
- 1),
382 AddrRange(pci_config_address_space_base
,
386 # Create a bridge from the IO bus to the memory bus to allow access to
387 # the local APIC (two pages)
388 x86_sys
.apicbridge
= Bridge(delay
='50ns', nack_delay
='4ns')
389 x86_sys
.apicbridge
.slave
= x86_sys
.iobus
.master
390 x86_sys
.apicbridge
.master
= x86_sys
.membus
.slave
391 x86_sys
.apicbridge
.ranges
= [AddrRange(interrupts_address_space_base
,
392 interrupts_address_space_base
+
393 numCPUs
* APIC_range_size
397 x86_sys
.pc
.attachIO(x86_sys
.iobus
)
399 x86_sys
.system_port
= x86_sys
.membus
.slave
401 def connectX86RubySystem(x86_sys
):
403 x86_sys
.piobus
= Bus(bus_id
=0)
406 # Pio functional accesses from devices need direct access to memory
407 # RubyPort currently does support functional accesses. Therefore provide
408 # the piobus a direct connection to physical memory
410 x86_sys
.piobus
.master
= x86_sys
.physmem
.port
412 x86_sys
.pc
.attachIO(x86_sys
.piobus
)
415 def makeX86System(mem_mode
, numCPUs
= 1, mdesc
= None, self
= None, Ruby
= False):
422 self
.readfile
= mdesc
.script()
424 self
.mem_mode
= mem_mode
427 self
.physmem
= PhysicalMemory(range = AddrRange(mdesc
.mem()))
432 # Create and connect the busses required by each memory system
434 connectX86RubySystem(self
)
435 # add the ide to the list of dma devices that later need to attach to
437 self
._dma
_devices
= [self
.pc
.south_bridge
.ide
]
439 connectX86ClassicSystem(self
, numCPUs
)
441 self
.intrctrl
= IntrControl()
444 disk0
= CowIdeDisk(driveID
='master')
445 disk2
= CowIdeDisk(driveID
='master')
446 disk0
.childImage(mdesc
.disk())
447 disk2
.childImage(disk('linux-bigswap2.img'))
448 self
.pc
.south_bridge
.ide
.disks
= [disk0
, disk2
]
450 # Add in a Bios information structure.
451 structures
= [X86SMBiosBiosInformation()]
452 self
.smbios_table
.structures
= structures
454 # Set up the Intel MP table
457 for i
in xrange(numCPUs
):
458 bp
= X86IntelMPProcessor(
460 local_apic_version
= 0x14,
462 bootstrap
= (i
== 0))
463 base_entries
.append(bp
)
464 io_apic
= X86IntelMPIOAPIC(
468 address
= 0xfec00000)
469 self
.pc
.south_bridge
.io_apic
.apic_id
= io_apic
.id
470 base_entries
.append(io_apic
)
471 isa_bus
= X86IntelMPBus(bus_id
= 0, bus_type
='ISA')
472 base_entries
.append(isa_bus
)
473 pci_bus
= X86IntelMPBus(bus_id
= 1, bus_type
='PCI')
474 base_entries
.append(pci_bus
)
475 connect_busses
= X86IntelMPBusHierarchy(bus_id
=0,
476 subtractive_decode
=True, parent_bus
=1)
477 ext_entries
.append(connect_busses
)
478 pci_dev4_inta
= X86IntelMPIOIntAssignment(
479 interrupt_type
= 'INT',
480 polarity
= 'ConformPolarity',
481 trigger
= 'ConformTrigger',
483 source_bus_irq
= 0 + (4 << 2),
484 dest_io_apic_id
= io_apic
.id,
485 dest_io_apic_intin
= 16)
486 base_entries
.append(pci_dev4_inta
)
487 def assignISAInt(irq
, apicPin
):
488 assign_8259_to_apic
= X86IntelMPIOIntAssignment(
489 interrupt_type
= 'ExtInt',
490 polarity
= 'ConformPolarity',
491 trigger
= 'ConformTrigger',
493 source_bus_irq
= irq
,
494 dest_io_apic_id
= io_apic
.id,
495 dest_io_apic_intin
= 0)
496 base_entries
.append(assign_8259_to_apic
)
497 assign_to_apic
= X86IntelMPIOIntAssignment(
498 interrupt_type
= 'INT',
499 polarity
= 'ConformPolarity',
500 trigger
= 'ConformTrigger',
502 source_bus_irq
= irq
,
503 dest_io_apic_id
= io_apic
.id,
504 dest_io_apic_intin
= apicPin
)
505 base_entries
.append(assign_to_apic
)
508 for i
in range(3, 15):
510 self
.intel_mp_table
.base_entries
= base_entries
511 self
.intel_mp_table
.ext_entries
= ext_entries
513 def setWorkCountOptions(system
, options
):
514 if options
.work_item_id
!= None:
515 system
.work_item_id
= options
.work_item_id
516 if options
.work_begin_cpu_id_exit
!= None:
517 system
.work_begin_cpu_id_exit
= options
.work_begin_cpu_id_exit
518 if options
.work_end_exit_count
!= None:
519 system
.work_end_exit_count
= options
.work_end_exit_count
520 if options
.work_end_checkpoint_count
!= None:
521 system
.work_end_ckpt_count
= options
.work_end_checkpoint_count
522 if options
.work_begin_exit_count
!= None:
523 system
.work_begin_exit_count
= options
.work_begin_exit_count
524 if options
.work_begin_checkpoint_count
!= None:
525 system
.work_begin_ckpt_count
= options
.work_begin_checkpoint_count
526 if options
.work_cpus_checkpoint_count
!= None:
527 system
.work_cpus_ckpt_count
= options
.work_cpus_checkpoint_count
530 def makeLinuxX86System(mem_mode
, numCPUs
= 1, mdesc
= None, Ruby
= False):
531 self
= LinuxX86System()
533 # Build up the x86 system and then specialize it for Linux
534 makeX86System(mem_mode
, numCPUs
, mdesc
, self
, Ruby
)
536 # We assume below that there's at least 1MB of memory. We'll require 2
537 # just to avoid corner cases.
538 assert(self
.physmem
.range.second
.getValue() >= 0x200000)
540 self
.e820_table
.entries
= \
542 # Mark the first megabyte of memory as reserved
543 X86E820Entry(addr
= 0, size
= '1MB', range_type
= 2),
544 # Mark the rest as available
545 X86E820Entry(addr
= 0x100000,
546 size
= '%dB' % (self
.physmem
.range.second
- 0x100000 + 1),
551 self
.boot_osflags
= 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
556 def makeDualRoot(full_system
, testSystem
, driveSystem
, dumpfile
):
557 self
= Root(full_system
= full_system
)
558 self
.testsys
= testSystem
559 self
.drivesys
= driveSystem
560 self
.etherlink
= EtherLink()
561 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
562 self
.etherlink
.int1
= Parent
.drivesys
.tsunami
.ethernet
.interface
564 if hasattr(testSystem
, 'realview'):
565 self
.etherlink
.int0
= Parent
.testsys
.realview
.ethernet
.interface
566 self
.etherlink
.int1
= Parent
.drivesys
.realview
.ethernet
.interface
567 elif hasattr(testSystem
, 'tsunami'):
568 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
569 self
.etherlink
.int1
= Parent
.drivesys
.tsunami
.ethernet
.interface
571 fatal("Don't know how to connect these system together")
574 self
.etherdump
= EtherDump(file=dumpfile
)
575 self
.etherlink
.dump
= Parent
.etherdump
579 def setMipsOptions(TestCPUClass
):
581 TestCPUClass
.CoreParams
.CP0_PRId_CompanyOptions
= 0
582 TestCPUClass
.CoreParams
.CP0_PRId_CompanyID
= 1
583 TestCPUClass
.CoreParams
.CP0_PRId_ProcessorID
= 147
584 TestCPUClass
.CoreParams
.CP0_PRId_Revision
= 0
586 #CP0 Interrupt Control
587 TestCPUClass
.CoreParams
.CP0_IntCtl_IPTI
= 7
588 TestCPUClass
.CoreParams
.CP0_IntCtl_IPPCI
= 7
591 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
592 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
593 TestCPUClass
.CoreParams
.CP0_Config_BE
= 0 # Little Endian
594 TestCPUClass
.CoreParams
.CP0_Config_AR
= 1 # Architecture Revision 2
595 TestCPUClass
.CoreParams
.CP0_Config_AT
= 0 # MIPS32
596 TestCPUClass
.CoreParams
.CP0_Config_MT
= 1 # TLB MMU
597 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
600 TestCPUClass
.CoreParams
.CP0_Config1_M
= 1 # Config2 Implemented
601 TestCPUClass
.CoreParams
.CP0_Config1_MMU
= 63 # TLB Size
602 # ***VERY IMPORTANT***
603 # Remember to modify CP0_Config1 according to cache specs
604 # Examine file ../common/Cache.py
605 TestCPUClass
.CoreParams
.CP0_Config1_IS
= 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
606 TestCPUClass
.CoreParams
.CP0_Config1_IL
= 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
607 TestCPUClass
.CoreParams
.CP0_Config1_IA
= 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
608 TestCPUClass
.CoreParams
.CP0_Config1_DS
= 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
609 TestCPUClass
.CoreParams
.CP0_Config1_DL
= 5 # D-Cache Line Size, default is 64, i.e., 5
610 TestCPUClass
.CoreParams
.CP0_Config1_DA
= 1 # D-Cache Associativity, default is 2, i.e. 1
611 TestCPUClass
.CoreParams
.CP0_Config1_C2
= 0 # Coprocessor 2 not implemented(?)
612 TestCPUClass
.CoreParams
.CP0_Config1_MD
= 0 # MDMX ASE not implemented in Mips32
613 TestCPUClass
.CoreParams
.CP0_Config1_PC
= 1 # Performance Counters Implemented
614 TestCPUClass
.CoreParams
.CP0_Config1_WR
= 0 # Watch Registers Implemented
615 TestCPUClass
.CoreParams
.CP0_Config1_CA
= 0 # Mips16e NOT implemented
616 TestCPUClass
.CoreParams
.CP0_Config1_EP
= 0 # EJTag Not Implemented
617 TestCPUClass
.CoreParams
.CP0_Config1_FP
= 0 # FPU Implemented
620 TestCPUClass
.CoreParams
.CP0_Config2_M
= 1 # Config3 Implemented
621 TestCPUClass
.CoreParams
.CP0_Config2_TU
= 0 # Tertiary Cache Control
622 TestCPUClass
.CoreParams
.CP0_Config2_TS
= 0 # Tertiary Cache Sets Per Way
623 TestCPUClass
.CoreParams
.CP0_Config2_TL
= 0 # Tertiary Cache Line Size
624 TestCPUClass
.CoreParams
.CP0_Config2_TA
= 0 # Tertiary Cache Associativity
625 TestCPUClass
.CoreParams
.CP0_Config2_SU
= 0 # Secondary Cache Control
626 TestCPUClass
.CoreParams
.CP0_Config2_SS
= 0 # Secondary Cache Sets Per Way
627 TestCPUClass
.CoreParams
.CP0_Config2_SL
= 0 # Secondary Cache Line Size
628 TestCPUClass
.CoreParams
.CP0_Config2_SA
= 0 # Secondary Cache Associativity
632 TestCPUClass
.CoreParams
.CP0_Config3_M
= 0 # Config4 Not Implemented
633 TestCPUClass
.CoreParams
.CP0_Config3_DSPP
= 1 # DSP ASE Present
634 TestCPUClass
.CoreParams
.CP0_Config3_LPA
= 0 # Large Physical Addresses Not supported in Mips32
635 TestCPUClass
.CoreParams
.CP0_Config3_VEIC
= 0 # EIC Supported
636 TestCPUClass
.CoreParams
.CP0_Config3_VInt
= 0 # Vectored Interrupts Implemented
637 TestCPUClass
.CoreParams
.CP0_Config3_SP
= 0 # Small Pages Supported (PageGrain reg. exists)
638 TestCPUClass
.CoreParams
.CP0_Config3_MT
= 0 # MT Not present
639 TestCPUClass
.CoreParams
.CP0_Config3_SM
= 0 # SmartMIPS ASE Not implemented
640 TestCPUClass
.CoreParams
.CP0_Config3_TL
= 0 # TraceLogic Not implemented
643 TestCPUClass
.CoreParams
.CP0_SrsCtl_HSS
= 3 # Four shadow register sets implemented
646 #TestCPUClass.CoreParams.tlb = TLB()
647 #TestCPUClass.CoreParams.UnifiedTLB = 1