configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Kevin Lim
  41
  42 from m5.objects import *
  43 from Benchmarks import *
  44 from m5.util import convert
  45
  46 class CowIdeDisk(IdeDisk):
  47     image = CowDiskImage(child=RawDiskImage(read_only=True),
  48                          read_only=False)
  49
  50     def childImage(self, ci):
  51         self.image.child.image_file = ci
  52
  53 class MemBus(CoherentBus):
  54     badaddr_responder = BadAddr()
  55     default = Self.badaddr_responder.pio
  56
  57
  58 def makeLinuxAlphaSystem(mem_mode, mdesc = None):
  59     IO_address_space_base = 0x80000000000
  60     class BaseTsunami(Tsunami):
  61         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  62         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  63                             pci_func=0, pci_dev=0, pci_bus=0)
  64
  65     self = LinuxAlphaSystem()
  66     if not mdesc:
  67         # generic system
  68         mdesc = SysConfig()
  69     self.readfile = mdesc.script()
  70     self.iobus = NoncoherentBus()
  71     self.membus = MemBus()
  72     # By default the bridge responds to all addresses above the I/O
  73     # base address (including the PCI config space)
  74     self.bridge = Bridge(delay='50ns',
  75                          ranges = [AddrRange(IO_address_space_base, Addr.max)])
  76     self.mem_ranges = [AddrRange(mdesc.mem())]
  77     self.bridge.master = self.iobus.slave
  78     self.bridge.slave = self.membus.master
  79     self.disk0 = CowIdeDisk(driveID='master')
  80     self.disk2 = CowIdeDisk(driveID='master')
  81     self.disk0.childImage(mdesc.disk())
  82     self.disk2.childImage(disk('linux-bigswap2.img'))
  83     self.tsunami = BaseTsunami()
  84     self.tsunami.attachIO(self.iobus)
  85     self.tsunami.ide.pio = self.iobus.master
  86     self.tsunami.ide.config = self.iobus.master
  87     self.tsunami.ide.dma = self.iobus.slave
  88     self.tsunami.ethernet.pio = self.iobus.master
  89     self.tsunami.ethernet.config = self.iobus.master
  90     self.tsunami.ethernet.dma = self.iobus.slave
  91     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
  92                                                read_only = True))
  93     self.intrctrl = IntrControl()
  94     self.mem_mode = mem_mode
  95     self.terminal = Terminal()
  96     self.kernel = binary('vmlinux')
  97     self.pal = binary('ts_osfpal')
  98     self.console = binary('console')
  99     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 100
 101     self.system_port = self.membus.slave
 102
 103     return self
 104
 105 def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
 106     class BaseTsunami(Tsunami):
 107         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 108         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 109                             pci_func=0, pci_dev=0, pci_bus=0)
 110     self = LinuxAlphaSystem()
 111     self.mem_ranges = [AddrRange(mdesc.mem())]
 112     if not mdesc:
 113         # generic system
 114         mdesc = SysConfig()
 115     self.readfile = mdesc.script()
 116
 117     # Create pio bus to connect all device pio ports to rubymem's pio port
 118     self.piobus = NoncoherentBus()
 119
 120     self.disk0 = CowIdeDisk(driveID='master')
 121     self.disk2 = CowIdeDisk(driveID='master')
 122     self.disk0.childImage(mdesc.disk())
 123     self.disk2.childImage(disk('linux-bigswap2.img'))
 124     self.tsunami = BaseTsunami()
 125     self.tsunami.attachIO(self.piobus)
 126     self.tsunami.ide.pio = self.piobus.master
 127     self.tsunami.ide.config = self.piobus.master
 128     self.tsunami.ethernet.pio = self.piobus.master
 129     self.tsunami.ethernet.config = self.piobus.master
 130
 131     #
 132     # Store the dma devices for later connection to dma ruby ports.
 133     # Append an underscore to dma_devices to avoid the SimObjectVector check.
 134     #
 135     self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
 136
 137     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 138                                                read_only = True))
 139     self.intrctrl = IntrControl()
 140     self.mem_mode = mem_mode
 141     self.terminal = Terminal()
 142     self.kernel = binary('vmlinux')
 143     self.pal = binary('ts_osfpal')
 144     self.console = binary('console')
 145     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 146
 147     return self
 148
 149 def makeSparcSystem(mem_mode, mdesc = None):
 150     # Constants from iob.cc and uart8250.cc
 151     iob_man_addr = 0x9800000000
 152     uart_pio_size = 8
 153
 154     class CowMmDisk(MmDisk):
 155         image = CowDiskImage(child=RawDiskImage(read_only=True),
 156                              read_only=False)
 157
 158         def childImage(self, ci):
 159             self.image.child.image_file = ci
 160
 161     self = SparcSystem()
 162     if not mdesc:
 163         # generic system
 164         mdesc = SysConfig()
 165     self.readfile = mdesc.script()
 166     self.iobus = NoncoherentBus()
 167     self.membus = MemBus()
 168     self.bridge = Bridge(delay='50ns')
 169     self.t1000 = T1000()
 170     self.t1000.attachOnChipIO(self.membus)
 171     self.t1000.attachIO(self.iobus)
 172     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 173                        AddrRange(Addr('2GB'), size ='256MB')]
 174     self.bridge.master = self.iobus.slave
 175     self.bridge.slave = self.membus.master
 176     self.rom.port = self.membus.master
 177     self.nvram.port = self.membus.master
 178     self.hypervisor_desc.port = self.membus.master
 179     self.partition_desc.port = self.membus.master
 180     self.intrctrl = IntrControl()
 181     self.disk0 = CowMmDisk()
 182     self.disk0.childImage(disk('disk.s10hw2'))
 183     self.disk0.pio = self.iobus.master
 184
 185     # The puart0 and hvuart are placed on the IO bus, so create ranges
 186     # for them. The remaining IO range is rather fragmented, so poke
 187     # holes for the iob and partition descriptors etc.
 188     self.bridge.ranges = \
 189         [
 190         AddrRange(self.t1000.puart0.pio_addr,
 191                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 192         AddrRange(self.disk0.pio_addr,
 193                   self.t1000.fake_jbi.pio_addr +
 194                   self.t1000.fake_jbi.pio_size - 1),
 195         AddrRange(self.t1000.fake_clk.pio_addr,
 196                   iob_man_addr - 1),
 197         AddrRange(self.t1000.fake_l2_1.pio_addr,
 198                   self.t1000.fake_ssi.pio_addr +
 199                   self.t1000.fake_ssi.pio_size - 1),
 200         AddrRange(self.t1000.hvuart.pio_addr,
 201                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 202         ]
 203     self.reset_bin = binary('reset_new.bin')
 204     self.hypervisor_bin = binary('q_new.bin')
 205     self.openboot_bin = binary('openboot_new.bin')
 206     self.nvram_bin = binary('nvram1')
 207     self.hypervisor_desc_bin = binary('1up-hv.bin')
 208     self.partition_desc_bin = binary('1up-md.bin')
 209
 210     self.system_port = self.membus.slave
 211
 212     return self
 213
 214 def makeArmSystem(mem_mode, machine_type, mdesc = None,
 215                   dtb_filename = None, bare_metal=False):
 216     assert machine_type
 217
 218     if bare_metal:
 219         self = ArmSystem()
 220     else:
 221         self = LinuxArmSystem()
 222
 223     if not mdesc:
 224         # generic system
 225         mdesc = SysConfig()
 226
 227     self.readfile = mdesc.script()
 228     self.iobus = NoncoherentBus()
 229     self.membus = MemBus()
 230     self.membus.badaddr_responder.warn_access = "warn"
 231     self.bridge = Bridge(delay='50ns')
 232     self.bridge.master = self.iobus.slave
 233     self.bridge.slave = self.membus.master
 234
 235     self.mem_mode = mem_mode
 236
 237     if machine_type == "RealView_PBX":
 238         self.realview = RealViewPBX()
 239     elif machine_type == "RealView_EB":
 240         self.realview = RealViewEB()
 241     elif machine_type == "VExpress_ELT":
 242         self.realview = VExpress_ELT()
 243     elif machine_type == "VExpress_EMM":
 244         self.realview = VExpress_EMM()
 245     elif machine_type == "VExpress_EMM64":
 246         self.realview = VExpress_EMM64()
 247     else:
 248         print "Unknown Machine Type"
 249         sys.exit(1)
 250
 251     self.cf0 = CowIdeDisk(driveID='master')
 252     self.cf0.childImage(mdesc.disk())
 253     # default to an IDE controller rather than a CF one
 254     # assuming we've got one
 255     try:
 256         self.realview.ide.disks = [self.cf0]
 257     except:
 258         self.realview.cf_ctrl.disks = [self.cf0]
 259
 260     if bare_metal:
 261         # EOT character on UART will end the simulation
 262         self.realview.uart.end_on_eot = True
 263         self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
 264                                      size = mdesc.mem())]
 265     else:
 266         self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
 267         if dtb_filename:
 268             self.dtb_filename = binary(dtb_filename)
 269         self.machine_type = machine_type
 270         if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
 271             print "The currently selected ARM platforms doesn't support"
 272             print " the amount of DRAM you've selected. Please try"
 273             print " another platform"
 274             sys.exit(1)
 275
 276         boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
 277                      'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
 278         self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
 279                                      size = mdesc.mem())]
 280         self.realview.setupBootLoader(self.membus, self, binary)
 281         self.gic_cpu_addr = self.realview.gic.cpu_addr
 282         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 283
 284         if mdesc.disk().lower().count('android'):
 285             boot_flags += " init=/init "
 286         self.boot_osflags = boot_flags
 287     self.realview.attachOnChipIO(self.membus, self.bridge)
 288     self.realview.attachIO(self.iobus)
 289     self.intrctrl = IntrControl()
 290     self.terminal = Terminal()
 291     self.vncserver = VncServer()
 292
 293     self.system_port = self.membus.slave
 294
 295     return self
 296
 297
 298 def makeLinuxMipsSystem(mem_mode, mdesc = None):
 299     class BaseMalta(Malta):
 300         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 301         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 302                             pci_func=0, pci_dev=0, pci_bus=0)
 303
 304     self = LinuxMipsSystem()
 305     if not mdesc:
 306         # generic system
 307         mdesc = SysConfig()
 308     self.readfile = mdesc.script()
 309     self.iobus = NoncoherentBus()
 310     self.membus = MemBus()
 311     self.bridge = Bridge(delay='50ns')
 312     self.mem_ranges = [AddrRange('1GB')]
 313     self.bridge.master = self.iobus.slave
 314     self.bridge.slave = self.membus.master
 315     self.disk0 = CowIdeDisk(driveID='master')
 316     self.disk2 = CowIdeDisk(driveID='master')
 317     self.disk0.childImage(mdesc.disk())
 318     self.disk2.childImage(disk('linux-bigswap2.img'))
 319     self.malta = BaseMalta()
 320     self.malta.attachIO(self.iobus)
 321     self.malta.ide.pio = self.iobus.master
 322     self.malta.ide.config = self.iobus.master
 323     self.malta.ide.dma = self.iobus.slave
 324     self.malta.ethernet.pio = self.iobus.master
 325     self.malta.ethernet.config = self.iobus.master
 326     self.malta.ethernet.dma = self.iobus.slave
 327     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 328                                                read_only = True))
 329     self.intrctrl = IntrControl()
 330     self.mem_mode = mem_mode
 331     self.terminal = Terminal()
 332     self.kernel = binary('mips/vmlinux')
 333     self.console = binary('mips/console')
 334     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 335
 336     self.system_port = self.membus.slave
 337
 338     return self
 339
 340 def x86IOAddress(port):
 341     IO_address_space_base = 0x8000000000000000
 342     return IO_address_space_base + port
 343
 344 def connectX86ClassicSystem(x86_sys, numCPUs):
 345     # Constants similar to x86_traits.hh
 346     IO_address_space_base = 0x8000000000000000
 347     pci_config_address_space_base = 0xc000000000000000
 348     interrupts_address_space_base = 0xa000000000000000
 349     APIC_range_size = 1 << 12;
 350
 351     x86_sys.membus = MemBus()
 352
 353     # North Bridge
 354     x86_sys.iobus = NoncoherentBus()
 355     x86_sys.bridge = Bridge(delay='50ns')
 356     x86_sys.bridge.master = x86_sys.iobus.slave
 357     x86_sys.bridge.slave = x86_sys.membus.master
 358     # Allow the bridge to pass through the IO APIC (two pages),
 359     # everything in the IO address range up to the local APIC, and
 360     # then the entire PCI address space and beyond
 361     x86_sys.bridge.ranges = \
 362         [
 363         AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
 364                   x86_sys.pc.south_bridge.io_apic.pio_addr +
 365                   APIC_range_size - 1),
 366         AddrRange(IO_address_space_base,
 367                   interrupts_address_space_base - 1),
 368         AddrRange(pci_config_address_space_base,
 369                   Addr.max)
 370         ]
 371
 372     # Create a bridge from the IO bus to the memory bus to allow access to
 373     # the local APIC (two pages)
 374     x86_sys.apicbridge = Bridge(delay='50ns')
 375     x86_sys.apicbridge.slave = x86_sys.iobus.master
 376     x86_sys.apicbridge.master = x86_sys.membus.slave
 377     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 378                                            interrupts_address_space_base +
 379                                            numCPUs * APIC_range_size
 380                                            - 1)]
 381
 382     # connect the io bus
 383     x86_sys.pc.attachIO(x86_sys.iobus)
 384
 385     x86_sys.system_port = x86_sys.membus.slave
 386
 387 def connectX86RubySystem(x86_sys):
 388     # North Bridge
 389     x86_sys.piobus = NoncoherentBus()
 390
 391     # add the ide to the list of dma devices that later need to attach to
 392     # dma controllers
 393     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 394     x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
 395
 396
 397 def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
 398                   Ruby = False):
 399     if self == None:
 400         self = X86System()
 401
 402     if not mdesc:
 403         # generic system
 404         mdesc = SysConfig()
 405     self.readfile = mdesc.script()
 406
 407     self.mem_mode = mem_mode
 408
 409     # Physical memory
 410     self.mem_ranges = [AddrRange(mdesc.mem())]
 411
 412     # Platform
 413     self.pc = Pc()
 414
 415     # Create and connect the busses required by each memory system
 416     if Ruby:
 417         connectX86RubySystem(self)
 418     else:
 419         connectX86ClassicSystem(self, numCPUs)
 420
 421     self.intrctrl = IntrControl()
 422
 423     # Disks
 424     disk0 = CowIdeDisk(driveID='master')
 425     disk2 = CowIdeDisk(driveID='master')
 426     disk0.childImage(mdesc.disk())
 427     disk2.childImage(disk('linux-bigswap2.img'))
 428     self.pc.south_bridge.ide.disks = [disk0, disk2]
 429
 430     # Add in a Bios information structure.
 431     structures = [X86SMBiosBiosInformation()]
 432     self.smbios_table.structures = structures
 433
 434     # Set up the Intel MP table
 435     base_entries = []
 436     ext_entries = []
 437     for i in xrange(numCPUs):
 438         bp = X86IntelMPProcessor(
 439                 local_apic_id = i,
 440                 local_apic_version = 0x14,
 441                 enable = True,
 442                 bootstrap = (i == 0))
 443         base_entries.append(bp)
 444     io_apic = X86IntelMPIOAPIC(
 445             id = numCPUs,
 446             version = 0x11,
 447             enable = True,
 448             address = 0xfec00000)
 449     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 450     base_entries.append(io_apic)
 451     isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
 452     base_entries.append(isa_bus)
 453     pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
 454     base_entries.append(pci_bus)
 455     connect_busses = X86IntelMPBusHierarchy(bus_id=0,
 456             subtractive_decode=True, parent_bus=1)
 457     ext_entries.append(connect_busses)
 458     pci_dev4_inta = X86IntelMPIOIntAssignment(
 459             interrupt_type = 'INT',
 460             polarity = 'ConformPolarity',
 461             trigger = 'ConformTrigger',
 462             source_bus_id = 1,
 463             source_bus_irq = 0 + (4 << 2),
 464             dest_io_apic_id = io_apic.id,
 465             dest_io_apic_intin = 16)
 466     base_entries.append(pci_dev4_inta)
 467     def assignISAInt(irq, apicPin):
 468         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 469                 interrupt_type = 'ExtInt',
 470                 polarity = 'ConformPolarity',
 471                 trigger = 'ConformTrigger',
 472                 source_bus_id = 0,
 473                 source_bus_irq = irq,
 474                 dest_io_apic_id = io_apic.id,
 475                 dest_io_apic_intin = 0)
 476         base_entries.append(assign_8259_to_apic)
 477         assign_to_apic = X86IntelMPIOIntAssignment(
 478                 interrupt_type = 'INT',
 479                 polarity = 'ConformPolarity',
 480                 trigger = 'ConformTrigger',
 481                 source_bus_id = 0,
 482                 source_bus_irq = irq,
 483                 dest_io_apic_id = io_apic.id,
 484                 dest_io_apic_intin = apicPin)
 485         base_entries.append(assign_to_apic)
 486     assignISAInt(0, 2)
 487     assignISAInt(1, 1)
 488     for i in range(3, 15):
 489         assignISAInt(i, i)
 490     self.intel_mp_table.base_entries = base_entries
 491     self.intel_mp_table.ext_entries = ext_entries
 492
 493 def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
 494                        Ruby = False):
 495     self = LinuxX86System()
 496
 497     # Build up the x86 system and then specialize it for Linux
 498     makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 499
 500     # We assume below that there's at least 1MB of memory. We'll require 2
 501     # just to avoid corner cases.
 502     phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
 503     assert(phys_mem_size >= 0x200000)
 504
 505     self.e820_table.entries = \
 506        [
 507         # Mark the first megabyte of memory as reserved
 508         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 509         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 510         # Mark the rest as available
 511         X86E820Entry(addr = 0x100000,
 512                 size = '%dB' % (phys_mem_size - 0x100000),
 513                 range_type = 1),
 514         # Reserve the last 16kB of the 32-bit address space for the
 515         # m5op interface
 516         X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
 517         ]
 518
 519     # Command line
 520     self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
 521                         'root=/dev/hda1'
 522     self.kernel = binary('x86_64-vmlinux-2.6.22.9')
 523     return self
 524
 525
 526 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 527     self = Root(full_system = full_system)
 528     self.testsys = testSystem
 529     self.drivesys = driveSystem
 530     self.etherlink = EtherLink()
 531     self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 532     self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 533
 534     if hasattr(testSystem, 'realview'):
 535         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 536         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 537     elif hasattr(testSystem, 'tsunami'):
 538         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 539         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 540     else:
 541         fatal("Don't know how to connect these system together")
 542
 543     if dumpfile:
 544         self.etherdump = EtherDump(file=dumpfile)
 545         self.etherlink.dump = Parent.etherdump
 546
 547     return self