configs/common/FSConfig.py

   1 # Copyright (c) 2010 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Kevin Lim
  41
  42 from m5.objects import *
  43 from Benchmarks import *
  44
  45 class CowIdeDisk(IdeDisk):
  46     image = CowDiskImage(child=RawDiskImage(read_only=True),
  47                          read_only=False)
  48
  49     def childImage(self, ci):
  50         self.image.child.image_file = ci
  51
  52 class MemBus(Bus):
  53     badaddr_responder = BadAddr()
  54     default = Self.badaddr_responder.pio
  55
  56
  57 def makeLinuxAlphaSystem(mem_mode, mdesc = None):
  58     class BaseTsunami(Tsunami):
  59         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  60         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  61                             pci_func=0, pci_dev=0, pci_bus=0)
  62
  63     self = LinuxAlphaSystem()
  64     if not mdesc:
  65         # generic system
  66         mdesc = SysConfig()
  67     self.readfile = mdesc.script()
  68     self.iobus = Bus(bus_id=0)
  69     self.membus = MemBus(bus_id=1)
  70     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
  71     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
  72     self.bridge.side_a = self.iobus.port
  73     self.bridge.side_b = self.membus.port
  74     self.physmem.port = self.membus.port
  75     self.disk0 = CowIdeDisk(driveID='master')
  76     self.disk2 = CowIdeDisk(driveID='master')
  77     self.disk0.childImage(mdesc.disk())
  78     self.disk2.childImage(disk('linux-bigswap2.img'))
  79     self.tsunami = BaseTsunami()
  80     self.tsunami.attachIO(self.iobus)
  81     self.tsunami.ide.pio = self.iobus.port
  82     self.tsunami.ethernet.pio = self.iobus.port
  83     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
  84                                                read_only = True))
  85     self.intrctrl = IntrControl()
  86     self.mem_mode = mem_mode
  87     self.terminal = Terminal()
  88     self.kernel = binary('vmlinux')
  89     self.pal = binary('ts_osfpal')
  90     self.console = binary('console')
  91     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
  92
  93     return self
  94
  95 def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
  96     class BaseTsunami(Tsunami):
  97         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  98         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  99                             pci_func=0, pci_dev=0, pci_bus=0)
 100
 101     physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
 102     self = LinuxAlphaSystem(physmem = physmem)
 103     if not mdesc:
 104         # generic system
 105         mdesc = SysConfig()
 106     self.readfile = mdesc.script()
 107
 108     # Create pio bus to connect all device pio ports to rubymem's pio port
 109     self.piobus = Bus(bus_id=0)
 110
 111     #
 112     # Pio functional accesses from devices need direct access to memory
 113     # RubyPort currently does support functional accesses.  Therefore provide
 114     # the piobus a direct connection to physical memory
 115     #
 116     self.piobus.port = physmem.port
 117
 118     self.disk0 = CowIdeDisk(driveID='master')
 119     self.disk2 = CowIdeDisk(driveID='master')
 120     self.disk0.childImage(mdesc.disk())
 121     self.disk2.childImage(disk('linux-bigswap2.img'))
 122     self.tsunami = BaseTsunami()
 123     self.tsunami.attachIO(self.piobus)
 124     self.tsunami.ide.pio = self.piobus.port
 125     self.tsunami.ethernet.pio = self.piobus.port
 126
 127     #
 128     # Store the dma devices for later connection to dma ruby ports.
 129     # Append an underscore to dma_devices to avoid the SimObjectVector check.
 130     #
 131     self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
 132
 133     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 134                                                read_only = True))
 135     self.intrctrl = IntrControl()
 136     self.mem_mode = mem_mode
 137     self.terminal = Terminal()
 138     self.kernel = binary('vmlinux')
 139     self.pal = binary('ts_osfpal')
 140     self.console = binary('console')
 141     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 142
 143     return self
 144
 145 def makeSparcSystem(mem_mode, mdesc = None):
 146     class CowMmDisk(MmDisk):
 147         image = CowDiskImage(child=RawDiskImage(read_only=True),
 148                              read_only=False)
 149
 150         def childImage(self, ci):
 151             self.image.child.image_file = ci
 152
 153     self = SparcSystem()
 154     if not mdesc:
 155         # generic system
 156         mdesc = SysConfig()
 157     self.readfile = mdesc.script()
 158     self.iobus = Bus(bus_id=0)
 159     self.membus = MemBus(bus_id=1)
 160     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 161     self.t1000 = T1000()
 162     self.t1000.attachOnChipIO(self.membus)
 163     self.t1000.attachIO(self.iobus)
 164     self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
 165     self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
 166     self.bridge.side_a = self.iobus.port
 167     self.bridge.side_b = self.membus.port
 168     self.physmem.port = self.membus.port
 169     self.physmem2.port = self.membus.port
 170     self.rom.port = self.membus.port
 171     self.nvram.port = self.membus.port
 172     self.hypervisor_desc.port = self.membus.port
 173     self.partition_desc.port = self.membus.port
 174     self.intrctrl = IntrControl()
 175     self.disk0 = CowMmDisk()
 176     self.disk0.childImage(disk('disk.s10hw2'))
 177     self.disk0.pio = self.iobus.port
 178     self.reset_bin = binary('reset_new.bin')
 179     self.hypervisor_bin = binary('q_new.bin')
 180     self.openboot_bin = binary('openboot_new.bin')
 181     self.nvram_bin = binary('nvram1')
 182     self.hypervisor_desc_bin = binary('1up-hv.bin')
 183     self.partition_desc_bin = binary('1up-md.bin')
 184
 185     return self
 186
 187 def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False,
 188         machine_type = None):
 189     if bare_metal:
 190         self = ArmSystem()
 191     else:
 192         self = LinuxArmSystem()
 193
 194     if not mdesc:
 195         # generic system
 196         mdesc = SysConfig()
 197
 198     self.readfile = mdesc.script()
 199     self.iobus = Bus(bus_id=0)
 200     self.membus = MemBus(bus_id=1)
 201     self.membus.badaddr_responder.warn_access = "warn"
 202     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 203     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
 204     self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
 205                                   file = disk('ael-arm.ext2'))
 206     self.bridge.side_a = self.iobus.port
 207     self.bridge.side_b = self.membus.port
 208     self.physmem.port = self.membus.port
 209     self.diskmem.port = self.membus.port
 210
 211     self.mem_mode = mem_mode
 212
 213     #self.cf0 = CowIdeDisk(driveID='master')
 214     #self.cf0.childImage(mdesc.disk())
 215     #self.cf_ctrl = IdeController(disks=[self.cf0],
 216     #                             pci_func = 0, pci_dev = 0, pci_bus = 0,
 217     #                             io_shift = 1, ctrl_offset = 2, Command = 0x1,
 218     #                             BAR0 = 0x18000000, BAR0Size = '16B',
 219     #                             BAR1 = 0x18000100, BAR1Size = '1B',
 220     #                             BAR0LegacyIO = True, BAR1LegacyIO = True,)
 221     #self.cf_ctrl.pio = self.iobus.port
 222
 223     if machine_type == "RealView_PBX":
 224         self.realview = RealViewPBX()
 225     elif machine_type == "RealView_EB":
 226         self.realview = RealViewEB()
 227     else:
 228         print "Unknown Machine Type"
 229         sys.exit(1)
 230
 231     if not bare_metal and machine_type:
 232         self.machine_type = machine_type
 233     elif bare_metal:
 234         self.realview.uart.end_on_eot = True
 235
 236     self.realview.attachOnChipIO(self.membus)
 237     self.realview.attachIO(self.iobus)
 238
 239     self.intrctrl = IntrControl()
 240     self.terminal = Terminal()
 241     self.vncserver = VncServer()
 242     self.kernel = binary('vmlinux.arm')
 243     self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \
 244                         ' norandmaps slram=slram0,0x8000000,+0x8000000' +      \
 245                         ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
 246
 247     return self
 248
 249
 250 def makeLinuxMipsSystem(mem_mode, mdesc = None):
 251     class BaseMalta(Malta):
 252         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 253         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 254                             pci_func=0, pci_dev=0, pci_bus=0)
 255
 256     self = LinuxMipsSystem()
 257     if not mdesc:
 258         # generic system
 259         mdesc = SysConfig()
 260     self.readfile = mdesc.script()
 261     self.iobus = Bus(bus_id=0)
 262     self.membus = MemBus(bus_id=1)
 263     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 264     self.physmem = PhysicalMemory(range = AddrRange('1GB'))
 265     self.bridge.side_a = self.iobus.port
 266     self.bridge.side_b = self.membus.port
 267     self.physmem.port = self.membus.port
 268     self.disk0 = CowIdeDisk(driveID='master')
 269     self.disk2 = CowIdeDisk(driveID='master')
 270     self.disk0.childImage(mdesc.disk())
 271     self.disk2.childImage(disk('linux-bigswap2.img'))
 272     self.malta = BaseMalta()
 273     self.malta.attachIO(self.iobus)
 274     self.malta.ide.pio = self.iobus.port
 275     self.malta.ethernet.pio = self.iobus.port
 276     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 277                                                read_only = True))
 278     self.intrctrl = IntrControl()
 279     self.mem_mode = mem_mode
 280     self.terminal = Terminal()
 281     self.kernel = binary('mips/vmlinux')
 282     self.console = binary('mips/console')
 283     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 284
 285     return self
 286
 287 def x86IOAddress(port):
 288     IO_address_space_base = 0x8000000000000000
 289     return IO_address_space_base + port;
 290
 291 def connectX86ClassicSystem(x86_sys):
 292     x86_sys.membus = MemBus(bus_id=1)
 293     x86_sys.physmem.port = x86_sys.membus.port
 294
 295     # North Bridge
 296     x86_sys.iobus = Bus(bus_id=0)
 297     x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
 298     x86_sys.bridge.side_a = x86_sys.iobus.port
 299     x86_sys.bridge.side_b = x86_sys.membus.port
 300
 301     # connect the io bus
 302     x86_sys.pc.attachIO(x86_sys.iobus)
 303
 304 def connectX86RubySystem(x86_sys):
 305     # North Bridge
 306     x86_sys.piobus = Bus(bus_id=0)
 307
 308     #
 309     # Pio functional accesses from devices need direct access to memory
 310     # RubyPort currently does support functional accesses.  Therefore provide
 311     # the piobus a direct connection to physical memory
 312     #
 313     x86_sys.piobus.port = x86_sys.physmem.port
 314
 315     x86_sys.pc.attachIO(x86_sys.piobus)
 316
 317
 318 def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
 319     if self == None:
 320         self = X86System()
 321
 322     if not mdesc:
 323         # generic system
 324         mdesc = SysConfig()
 325     self.readfile = mdesc.script()
 326
 327     self.mem_mode = mem_mode
 328
 329     # Physical memory
 330     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
 331
 332     # Platform
 333     self.pc = Pc()
 334
 335     # Create and connect the busses required by each memory system
 336     if Ruby:
 337         connectX86RubySystem(self)
 338         # add the ide to the list of dma devices that later need to attach to
 339         # dma controllers
 340         self._dma_devices = [self.pc.south_bridge.ide]
 341     else:
 342         connectX86ClassicSystem(self)
 343
 344     self.intrctrl = IntrControl()
 345
 346     # Disks
 347     disk0 = CowIdeDisk(driveID='master')
 348     disk2 = CowIdeDisk(driveID='master')
 349     disk0.childImage(mdesc.disk())
 350     disk2.childImage(disk('linux-bigswap2.img'))
 351     self.pc.south_bridge.ide.disks = [disk0, disk2]
 352
 353     # Add in a Bios information structure.
 354     structures = [X86SMBiosBiosInformation()]
 355     self.smbios_table.structures = structures
 356
 357     # Set up the Intel MP table
 358     for i in xrange(numCPUs):
 359         bp = X86IntelMPProcessor(
 360                 local_apic_id = i,
 361                 local_apic_version = 0x14,
 362                 enable = True,
 363                 bootstrap = (i == 0))
 364         self.intel_mp_table.add_entry(bp)
 365     io_apic = X86IntelMPIOAPIC(
 366             id = numCPUs,
 367             version = 0x11,
 368             enable = True,
 369             address = 0xfec00000)
 370     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 371     self.intel_mp_table.add_entry(io_apic)
 372     isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
 373     self.intel_mp_table.add_entry(isa_bus)
 374     pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
 375     self.intel_mp_table.add_entry(pci_bus)
 376     connect_busses = X86IntelMPBusHierarchy(bus_id=0,
 377             subtractive_decode=True, parent_bus=1)
 378     self.intel_mp_table.add_entry(connect_busses)
 379     pci_dev4_inta = X86IntelMPIOIntAssignment(
 380             interrupt_type = 'INT',
 381             polarity = 'ConformPolarity',
 382             trigger = 'ConformTrigger',
 383             source_bus_id = 1,
 384             source_bus_irq = 0 + (4 << 2),
 385             dest_io_apic_id = io_apic.id,
 386             dest_io_apic_intin = 16)
 387     self.intel_mp_table.add_entry(pci_dev4_inta);
 388     def assignISAInt(irq, apicPin):
 389         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 390                 interrupt_type = 'ExtInt',
 391                 polarity = 'ConformPolarity',
 392                 trigger = 'ConformTrigger',
 393                 source_bus_id = 0,
 394                 source_bus_irq = irq,
 395                 dest_io_apic_id = io_apic.id,
 396                 dest_io_apic_intin = 0)
 397         self.intel_mp_table.add_entry(assign_8259_to_apic)
 398         assign_to_apic = X86IntelMPIOIntAssignment(
 399                 interrupt_type = 'INT',
 400                 polarity = 'ConformPolarity',
 401                 trigger = 'ConformTrigger',
 402                 source_bus_id = 0,
 403                 source_bus_irq = irq,
 404                 dest_io_apic_id = io_apic.id,
 405                 dest_io_apic_intin = apicPin)
 406         self.intel_mp_table.add_entry(assign_to_apic)
 407     assignISAInt(0, 2)
 408     assignISAInt(1, 1)
 409     for i in range(3, 15):
 410         assignISAInt(i, i)
 411
 412 def setWorkCountOptions(system, options):
 413     if options.work_item_id != None:
 414         system.work_item_id = options.work_item_id
 415     if options.work_begin_cpu_id_exit != None:
 416         system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
 417     if options.work_end_exit_count != None:
 418         system.work_end_exit_count = options.work_end_exit_count
 419     if options.work_end_checkpoint_count != None:
 420         system.work_end_ckpt_count = options.work_end_checkpoint_count
 421     if options.work_begin_exit_count != None:
 422         system.work_begin_exit_count = options.work_begin_exit_count
 423     if options.work_begin_checkpoint_count != None:
 424         system.work_begin_ckpt_count = options.work_begin_checkpoint_count
 425     if options.work_cpus_checkpoint_count != None:
 426         system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
 427
 428
 429 def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
 430     self = LinuxX86System()
 431
 432     # Build up the x86 system and then specialize it for Linux
 433     makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 434
 435     # We assume below that there's at least 1MB of memory. We'll require 2
 436     # just to avoid corner cases.
 437     assert(self.physmem.range.second.getValue() >= 0x200000)
 438
 439     # Mark the first megabyte of memory as reserved
 440     self.e820_table.entries.append(X86E820Entry(
 441                 addr = 0,
 442                 size = '1MB',
 443                 range_type = 2))
 444
 445     # Mark the rest as available
 446     self.e820_table.entries.append(X86E820Entry(
 447                 addr = 0x100000,
 448                 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
 449                 range_type = 1))
 450
 451     # Command line
 452     self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
 453                         'root=/dev/hda1'
 454     return self
 455
 456
 457 def makeDualRoot(testSystem, driveSystem, dumpfile):
 458     self = Root()
 459     self.testsys = testSystem
 460     self.drivesys = driveSystem
 461     self.etherlink = EtherLink()
 462     self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 463     self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 464
 465     if dumpfile:
 466         self.etherdump = EtherDump(file=dumpfile)
 467         self.etherlink.dump = Parent.etherdump
 468
 469     return self
 470
 471 def setMipsOptions(TestCPUClass):
 472         #CP0 Configuration
 473         TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
 474         TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
 475         TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
 476         TestCPUClass.CoreParams.CP0_PRId_Revision = 0
 477
 478         #CP0 Interrupt Control
 479         TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
 480         TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
 481
 482         # Config Register
 483         #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
 484         #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
 485         TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
 486         TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
 487         TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
 488         TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
 489         #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
 490
 491         #Config 1 Register
 492         TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
 493         TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
 494         # ***VERY IMPORTANT***
 495         # Remember to modify CP0_Config1 according to cache specs
 496         # Examine file ../common/Cache.py
 497         TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
 498         TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
 499         TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
 500         TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
 501         TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
 502         TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
 503         TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
 504         TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
 505         TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
 506         TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
 507         TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
 508         TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
 509         TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
 510
 511         #Config 2 Register
 512         TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
 513         TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
 514         TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
 515         TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
 516         TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
 517         TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
 518         TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
 519         TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
 520         TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
 521
 522
 523         #Config 3 Register
 524         TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
 525         TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
 526         TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
 527         TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
 528         TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
 529         TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
 530         TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
 531         TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
 532         TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
 533
 534         #SRS Ctl - HSS
 535         TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
 536
 537
 538         #TestCPUClass.CoreParams.tlb = TLB()
 539         #TestCPUClass.CoreParams.UnifiedTLB = 1