configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012, 2015 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
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  22 # notice, this list of conditions and the following disclaimer in the
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  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Kevin Lim
  41
  42 from m5.objects import *
  43 from Benchmarks import *
  44 from m5.util import *
  45 import PlatformConfig
  46
  47 # Populate to reflect supported os types per target ISA
  48 os_types = { 'alpha' : [ 'linux' ],
  49              'mips'  : [ 'linux' ],
  50              'sparc' : [ 'linux' ],
  51              'x86'   : [ 'linux' ],
  52              'arm'   : [ 'linux',
  53                          'android-gingerbread',
  54                          'android-ics',
  55                          'android-jellybean',
  56                          'android-kitkat' ],
  57            }
  58
  59 class CowIdeDisk(IdeDisk):
  60     image = CowDiskImage(child=RawDiskImage(read_only=True),
  61                          read_only=False)
  62
  63     def childImage(self, ci):
  64         self.image.child.image_file = ci
  65
  66 class MemBus(SystemXBar):
  67     badaddr_responder = BadAddr()
  68     default = Self.badaddr_responder.pio
  69
  70 def fillInCmdline(mdesc, template, **kwargs):
  71     kwargs.setdefault('disk', mdesc.disk())
  72     kwargs.setdefault('rootdev', mdesc.rootdev())
  73     kwargs.setdefault('mem', mdesc.mem())
  74     kwargs.setdefault('script', mdesc.script())
  75     return template % kwargs
  76
  77 def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
  78
  79     class BaseTsunami(Tsunami):
  80         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  81         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  82                             pci_func=0, pci_dev=0, pci_bus=0)
  83
  84     self = LinuxAlphaSystem()
  85     if not mdesc:
  86         # generic system
  87         mdesc = SysConfig()
  88     self.readfile = mdesc.script()
  89
  90     self.tsunami = BaseTsunami()
  91
  92     # Create the io bus to connect all device ports
  93     self.iobus = IOXBar()
  94     self.tsunami.attachIO(self.iobus)
  95
  96     self.tsunami.ide.pio = self.iobus.master
  97
  98     self.tsunami.ethernet.pio = self.iobus.master
  99
 100     if ruby:
 101         # Store the dma devices for later connection to dma ruby ports.
 102         # Append an underscore to dma_ports to avoid the SimObjectVector check.
 103         self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
 104     else:
 105         self.membus = MemBus()
 106
 107         # By default the bridge responds to all addresses above the I/O
 108         # base address (including the PCI config space)
 109         IO_address_space_base = 0x80000000000
 110         self.bridge = Bridge(delay='50ns',
 111                          ranges = [AddrRange(IO_address_space_base, Addr.max)])
 112         self.bridge.master = self.iobus.slave
 113         self.bridge.slave = self.membus.master
 114
 115         self.tsunami.ide.dma = self.iobus.slave
 116         self.tsunami.ethernet.dma = self.iobus.slave
 117
 118         self.system_port = self.membus.slave
 119
 120     self.mem_ranges = [AddrRange(mdesc.mem())]
 121     self.disk0 = CowIdeDisk(driveID='master')
 122     self.disk2 = CowIdeDisk(driveID='master')
 123     self.disk0.childImage(mdesc.disk())
 124     self.disk2.childImage(disk('linux-bigswap2.img'))
 125     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 126                                                read_only = True))
 127     self.intrctrl = IntrControl()
 128     self.mem_mode = mem_mode
 129     self.terminal = Terminal()
 130     self.kernel = binary('vmlinux')
 131     self.pal = binary('ts_osfpal')
 132     self.console = binary('console')
 133     if not cmdline:
 134         cmdline = 'root=/dev/hda1 console=ttyS0'
 135     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 136
 137     return self
 138
 139 def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
 140     # Constants from iob.cc and uart8250.cc
 141     iob_man_addr = 0x9800000000
 142     uart_pio_size = 8
 143
 144     class CowMmDisk(MmDisk):
 145         image = CowDiskImage(child=RawDiskImage(read_only=True),
 146                              read_only=False)
 147
 148         def childImage(self, ci):
 149             self.image.child.image_file = ci
 150
 151     self = SparcSystem()
 152     if not mdesc:
 153         # generic system
 154         mdesc = SysConfig()
 155     self.readfile = mdesc.script()
 156     self.iobus = IOXBar()
 157     self.membus = MemBus()
 158     self.bridge = Bridge(delay='50ns')
 159     self.t1000 = T1000()
 160     self.t1000.attachOnChipIO(self.membus)
 161     self.t1000.attachIO(self.iobus)
 162     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 163                        AddrRange(Addr('2GB'), size ='256MB')]
 164     self.bridge.master = self.iobus.slave
 165     self.bridge.slave = self.membus.master
 166     self.rom.port = self.membus.master
 167     self.nvram.port = self.membus.master
 168     self.hypervisor_desc.port = self.membus.master
 169     self.partition_desc.port = self.membus.master
 170     self.intrctrl = IntrControl()
 171     self.disk0 = CowMmDisk()
 172     self.disk0.childImage(disk('disk.s10hw2'))
 173     self.disk0.pio = self.iobus.master
 174
 175     # The puart0 and hvuart are placed on the IO bus, so create ranges
 176     # for them. The remaining IO range is rather fragmented, so poke
 177     # holes for the iob and partition descriptors etc.
 178     self.bridge.ranges = \
 179         [
 180         AddrRange(self.t1000.puart0.pio_addr,
 181                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 182         AddrRange(self.disk0.pio_addr,
 183                   self.t1000.fake_jbi.pio_addr +
 184                   self.t1000.fake_jbi.pio_size - 1),
 185         AddrRange(self.t1000.fake_clk.pio_addr,
 186                   iob_man_addr - 1),
 187         AddrRange(self.t1000.fake_l2_1.pio_addr,
 188                   self.t1000.fake_ssi.pio_addr +
 189                   self.t1000.fake_ssi.pio_size - 1),
 190         AddrRange(self.t1000.hvuart.pio_addr,
 191                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 192         ]
 193     self.reset_bin = binary('reset_new.bin')
 194     self.hypervisor_bin = binary('q_new.bin')
 195     self.openboot_bin = binary('openboot_new.bin')
 196     self.nvram_bin = binary('nvram1')
 197     self.hypervisor_desc_bin = binary('1up-hv.bin')
 198     self.partition_desc_bin = binary('1up-md.bin')
 199
 200     self.system_port = self.membus.slave
 201
 202     return self
 203
 204 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 205                   dtb_filename=None, bare_metal=False, cmdline=None,
 206                   external_memory=""):
 207     assert machine_type
 208
 209     default_dtbs = {
 210         "RealViewEB": None,
 211         "RealViewPBX": None,
 212         "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus,
 213         "VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
 214     }
 215
 216     default_kernels = {
 217         "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8",
 218         "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8",
 219         "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
 220         "VExpress_EMM64": "vmlinux.aarch64.20140821",
 221     }
 222
 223     if bare_metal:
 224         self = ArmSystem()
 225     else:
 226         self = LinuxArmSystem()
 227
 228     if not mdesc:
 229         # generic system
 230         mdesc = SysConfig()
 231
 232     self.readfile = mdesc.script()
 233     self.iobus = IOXBar()
 234     self.membus = MemBus()
 235     self.membus.badaddr_responder.warn_access = "warn"
 236     self.bridge = Bridge(delay='50ns')
 237     self.bridge.master = self.iobus.slave
 238     self.bridge.slave = self.membus.master
 239
 240     self.mem_mode = mem_mode
 241
 242     platform_class = PlatformConfig.get(machine_type)
 243     # Resolve the real platform name, the original machine_type
 244     # variable might have been an alias.
 245     machine_type = platform_class.__name__
 246     self.realview = platform_class()
 247
 248     if not dtb_filename and not bare_metal:
 249         try:
 250             dtb_filename = default_dtbs[machine_type]
 251         except KeyError:
 252             fatal("No DTB specified and no default DTB known for '%s'" % \
 253                   machine_type)
 254
 255     if isinstance(self.realview, VExpress_EMM64):
 256         if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
 257             print "Selected 64-bit ARM architecture, updating default disk image..."
 258             mdesc.diskname = 'linaro-minimal-aarch64.img'
 259
 260     self.cf0 = CowIdeDisk(driveID='master')
 261     self.cf0.childImage(mdesc.disk())
 262
 263     # Attach any PCI devices this platform supports
 264     self.realview.attachPciDevices()
 265     # default to an IDE controller rather than a CF one
 266     try:
 267         self.realview.ide.disks = [self.cf0]
 268     except:
 269         self.realview.cf_ctrl.disks = [self.cf0]
 270
 271     self.mem_ranges = []
 272     size_remain = long(Addr(mdesc.mem()))
 273     for region in self.realview._mem_regions:
 274         if size_remain > long(region[1]):
 275             self.mem_ranges.append(AddrRange(region[0], size=region[1]))
 276             size_remain = size_remain - long(region[1])
 277         else:
 278             self.mem_ranges.append(AddrRange(region[0], size=size_remain))
 279             size_remain = 0
 280             break
 281         warn("Memory size specified spans more than one region. Creating" \
 282              " another memory controller for that range.")
 283
 284     if size_remain > 0:
 285         fatal("The currently selected ARM platforms doesn't support" \
 286               " the amount of DRAM you've selected. Please try" \
 287               " another platform")
 288
 289     if bare_metal:
 290         # EOT character on UART will end the simulation
 291         self.realview.uart.end_on_eot = True
 292     else:
 293         if machine_type in default_kernels:
 294             self.kernel = binary(default_kernels[machine_type])
 295
 296         if dtb_filename:
 297             self.dtb_filename = binary(dtb_filename)
 298
 299         self.machine_type = machine_type if machine_type in ArmMachineType.map \
 300                             else "DTOnly"
 301
 302         # Ensure that writes to the UART actually go out early in the boot
 303         if not cmdline:
 304             cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
 305                       'lpj=19988480 norandmaps rw loglevel=8 ' + \
 306                       'mem=%(mem)s root=%(rootdev)s'
 307
 308         # When using external memory, gem5 writes the boot loader to nvmem
 309         # and then SST will read from it, but SST can only get to nvmem from
 310         # iobus, as gem5's membus is only used for initialization and
 311         # SST doesn't use it.  Attaching nvmem to iobus solves this issue.
 312         # During initialization, system_port -> membus -> iobus -> nvmem.
 313         if external_memory:
 314             self.realview.setupBootLoader(self.iobus,  self, binary)
 315         else:
 316             self.realview.setupBootLoader(self.membus, self, binary)
 317         self.gic_cpu_addr = self.realview.gic.cpu_addr
 318         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 319
 320         # This check is for users who have previously put 'android' in
 321         # the disk image filename to tell the config scripts to
 322         # prepare the kernel with android-specific boot options. That
 323         # behavior has been replaced with a more explicit option per
 324         # the error message below. The disk can have any name now and
 325         # doesn't need to include 'android' substring.
 326         if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
 327             if 'android' not in mdesc.os_type():
 328                 fatal("It looks like you are trying to boot an Android " \
 329                       "platform.  To boot Android, you must specify " \
 330                       "--os-type with an appropriate Android release on " \
 331                       "the command line.")
 332
 333         # android-specific tweaks
 334         if 'android' in mdesc.os_type():
 335             # generic tweaks
 336             cmdline += " init=/init"
 337
 338             # release-specific tweaks
 339             if 'kitkat' in mdesc.os_type():
 340                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 341                            "android.bootanim=0"
 342
 343         self.boot_osflags = fillInCmdline(mdesc, cmdline)
 344
 345     if external_memory:
 346         # I/O traffic enters iobus
 347         self.external_io = ExternalMaster(port_data="external_io",
 348                                           port_type=external_memory)
 349         self.external_io.port = self.iobus.slave
 350
 351         # Ensure iocache only receives traffic destined for (actual) memory.
 352         self.iocache = ExternalSlave(port_data="iocache",
 353                                      port_type=external_memory,
 354                                      addr_ranges=self.mem_ranges)
 355         self.iocache.port = self.iobus.master
 356
 357         # Let system_port get to nvmem and nothing else.
 358         self.bridge.ranges = [self.realview.nvmem.range]
 359
 360         self.realview.attachOnChipIO(self.iobus)
 361     else:
 362         self.realview.attachOnChipIO(self.membus, self.bridge)
 363     self.realview.attachIO(self.iobus)
 364     self.intrctrl = IntrControl()
 365     self.terminal = Terminal()
 366     self.vncserver = VncServer()
 367
 368     self.system_port = self.membus.slave
 369
 370     return self
 371
 372
 373 def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
 374     class BaseMalta(Malta):
 375         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 376         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 377                             pci_func=0, pci_dev=0, pci_bus=0)
 378
 379     self = LinuxMipsSystem()
 380     if not mdesc:
 381         # generic system
 382         mdesc = SysConfig()
 383     self.readfile = mdesc.script()
 384     self.iobus = IOXBar()
 385     self.membus = MemBus()
 386     self.bridge = Bridge(delay='50ns')
 387     self.mem_ranges = [AddrRange('1GB')]
 388     self.bridge.master = self.iobus.slave
 389     self.bridge.slave = self.membus.master
 390     self.disk0 = CowIdeDisk(driveID='master')
 391     self.disk2 = CowIdeDisk(driveID='master')
 392     self.disk0.childImage(mdesc.disk())
 393     self.disk2.childImage(disk('linux-bigswap2.img'))
 394     self.malta = BaseMalta()
 395     self.malta.attachIO(self.iobus)
 396     self.malta.ide.pio = self.iobus.master
 397     self.malta.ide.dma = self.iobus.slave
 398     self.malta.ethernet.pio = self.iobus.master
 399     self.malta.ethernet.dma = self.iobus.slave
 400     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 401                                                read_only = True))
 402     self.intrctrl = IntrControl()
 403     self.mem_mode = mem_mode
 404     self.terminal = Terminal()
 405     self.kernel = binary('mips/vmlinux')
 406     self.console = binary('mips/console')
 407     if not cmdline:
 408         cmdline = 'root=/dev/hda1 console=ttyS0'
 409     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 410
 411     self.system_port = self.membus.slave
 412
 413     return self
 414
 415 def x86IOAddress(port):
 416     IO_address_space_base = 0x8000000000000000
 417     return IO_address_space_base + port
 418
 419 def connectX86ClassicSystem(x86_sys, numCPUs):
 420     # Constants similar to x86_traits.hh
 421     IO_address_space_base = 0x8000000000000000
 422     pci_config_address_space_base = 0xc000000000000000
 423     interrupts_address_space_base = 0xa000000000000000
 424     APIC_range_size = 1 << 12;
 425
 426     x86_sys.membus = MemBus()
 427
 428     # North Bridge
 429     x86_sys.iobus = IOXBar()
 430     x86_sys.bridge = Bridge(delay='50ns')
 431     x86_sys.bridge.master = x86_sys.iobus.slave
 432     x86_sys.bridge.slave = x86_sys.membus.master
 433     # Allow the bridge to pass through:
 434     #  1) kernel configured PCI device memory map address: address range
 435     #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
 436     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
 437     #  3) everything in the IO address range up to the local APIC, and
 438     #  4) then the entire PCI address space and beyond.
 439     x86_sys.bridge.ranges = \
 440         [
 441         AddrRange(0xC0000000, 0xFFFF0000),
 442         AddrRange(IO_address_space_base,
 443                   interrupts_address_space_base - 1),
 444         AddrRange(pci_config_address_space_base,
 445                   Addr.max)
 446         ]
 447
 448     # Create a bridge from the IO bus to the memory bus to allow access to
 449     # the local APIC (two pages)
 450     x86_sys.apicbridge = Bridge(delay='50ns')
 451     x86_sys.apicbridge.slave = x86_sys.iobus.master
 452     x86_sys.apicbridge.master = x86_sys.membus.slave
 453     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 454                                            interrupts_address_space_base +
 455                                            numCPUs * APIC_range_size
 456                                            - 1)]
 457
 458     # connect the io bus
 459     x86_sys.pc.attachIO(x86_sys.iobus)
 460
 461     x86_sys.system_port = x86_sys.membus.slave
 462
 463 def connectX86RubySystem(x86_sys):
 464     # North Bridge
 465     x86_sys.iobus = IOXBar()
 466
 467     # add the ide to the list of dma devices that later need to attach to
 468     # dma controllers
 469     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 470     x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
 471
 472
 473 def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
 474     if self == None:
 475         self = X86System()
 476
 477     if not mdesc:
 478         # generic system
 479         mdesc = SysConfig()
 480     self.readfile = mdesc.script()
 481
 482     self.mem_mode = mem_mode
 483
 484     # Physical memory
 485     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
 486     # for various devices.  Hence, if the physical memory size is greater than
 487     # 3GB, we need to split it into two parts.
 488     excess_mem_size = \
 489         convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
 490     if excess_mem_size <= 0:
 491         self.mem_ranges = [AddrRange(mdesc.mem())]
 492     else:
 493         warn("Physical memory size specified is %s which is greater than " \
 494              "3GB.  Twice the number of memory controllers would be " \
 495              "created."  % (mdesc.mem()))
 496
 497         self.mem_ranges = [AddrRange('3GB'),
 498             AddrRange(Addr('4GB'), size = excess_mem_size)]
 499
 500     # Platform
 501     self.pc = Pc()
 502
 503     # Create and connect the busses required by each memory system
 504     if Ruby:
 505         connectX86RubySystem(self)
 506     else:
 507         connectX86ClassicSystem(self, numCPUs)
 508
 509     self.intrctrl = IntrControl()
 510
 511     # Disks
 512     disk0 = CowIdeDisk(driveID='master')
 513     disk2 = CowIdeDisk(driveID='master')
 514     disk0.childImage(mdesc.disk())
 515     disk2.childImage(disk('linux-bigswap2.img'))
 516     self.pc.south_bridge.ide.disks = [disk0, disk2]
 517
 518     # Add in a Bios information structure.
 519     structures = [X86SMBiosBiosInformation()]
 520     self.smbios_table.structures = structures
 521
 522     # Set up the Intel MP table
 523     base_entries = []
 524     ext_entries = []
 525     for i in xrange(numCPUs):
 526         bp = X86IntelMPProcessor(
 527                 local_apic_id = i,
 528                 local_apic_version = 0x14,
 529                 enable = True,
 530                 bootstrap = (i == 0))
 531         base_entries.append(bp)
 532     io_apic = X86IntelMPIOAPIC(
 533             id = numCPUs,
 534             version = 0x11,
 535             enable = True,
 536             address = 0xfec00000)
 537     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 538     base_entries.append(io_apic)
 539     # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 540     # but linux kernel cannot config PCI device if it was not connected to PCI bus,
 541     # so we fix PCI bus id to 0, and ISA bus id to 1.
 542     pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
 543     base_entries.append(pci_bus)
 544     isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
 545     base_entries.append(isa_bus)
 546     connect_busses = X86IntelMPBusHierarchy(bus_id=1,
 547             subtractive_decode=True, parent_bus=0)
 548     ext_entries.append(connect_busses)
 549     pci_dev4_inta = X86IntelMPIOIntAssignment(
 550             interrupt_type = 'INT',
 551             polarity = 'ConformPolarity',
 552             trigger = 'ConformTrigger',
 553             source_bus_id = 0,
 554             source_bus_irq = 0 + (4 << 2),
 555             dest_io_apic_id = io_apic.id,
 556             dest_io_apic_intin = 16)
 557     base_entries.append(pci_dev4_inta)
 558     def assignISAInt(irq, apicPin):
 559         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 560                 interrupt_type = 'ExtInt',
 561                 polarity = 'ConformPolarity',
 562                 trigger = 'ConformTrigger',
 563                 source_bus_id = 1,
 564                 source_bus_irq = irq,
 565                 dest_io_apic_id = io_apic.id,
 566                 dest_io_apic_intin = 0)
 567         base_entries.append(assign_8259_to_apic)
 568         assign_to_apic = X86IntelMPIOIntAssignment(
 569                 interrupt_type = 'INT',
 570                 polarity = 'ConformPolarity',
 571                 trigger = 'ConformTrigger',
 572                 source_bus_id = 1,
 573                 source_bus_irq = irq,
 574                 dest_io_apic_id = io_apic.id,
 575                 dest_io_apic_intin = apicPin)
 576         base_entries.append(assign_to_apic)
 577     assignISAInt(0, 2)
 578     assignISAInt(1, 1)
 579     for i in range(3, 15):
 580         assignISAInt(i, i)
 581     self.intel_mp_table.base_entries = base_entries
 582     self.intel_mp_table.ext_entries = ext_entries
 583
 584 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
 585                        cmdline=None):
 586     self = LinuxX86System()
 587
 588     # Build up the x86 system and then specialize it for Linux
 589     makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 590
 591     # We assume below that there's at least 1MB of memory. We'll require 2
 592     # just to avoid corner cases.
 593     phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
 594     assert(phys_mem_size >= 0x200000)
 595     assert(len(self.mem_ranges) <= 2)
 596
 597     entries = \
 598        [
 599         # Mark the first megabyte of memory as reserved
 600         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 601         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 602         # Mark the rest of physical memory as available
 603         X86E820Entry(addr = 0x100000,
 604                 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
 605                 range_type = 1),
 606         ]
 607
 608     # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
 609     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
 610     # specific range can pass though bridge to iobus.
 611     if len(self.mem_ranges) == 1:
 612         entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
 613             size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
 614             range_type=2))
 615
 616     # Reserve the last 16kB of the 32-bit address space for the m5op interface
 617     entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
 618
 619     # In case the physical memory is greater than 3GB, we split it into two
 620     # parts and add a separate e820 entry for the second part.  This entry
 621     # starts at 0x100000000,  which is the first address after the space
 622     # reserved for devices.
 623     if len(self.mem_ranges) == 2:
 624         entries.append(X86E820Entry(addr = 0x100000000,
 625             size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
 626
 627     self.e820_table.entries = entries
 628
 629     # Command line
 630     if not cmdline:
 631         cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
 632     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 633     self.kernel = binary('x86_64-vmlinux-2.6.22.9')
 634     return self
 635
 636
 637 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 638     self = Root(full_system = full_system)
 639     self.testsys = testSystem
 640     self.drivesys = driveSystem
 641     self.etherlink = EtherLink()
 642
 643     if hasattr(testSystem, 'realview'):
 644         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 645         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 646     elif hasattr(testSystem, 'tsunami'):
 647         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 648         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 649     else:
 650         fatal("Don't know how to connect these system together")
 651
 652     if dumpfile:
 653         self.etherdump = EtherDump(file=dumpfile)
 654         self.etherlink.dump = Parent.etherdump
 655
 656     return self
 657
 658
 659 def makeDistRoot(testSystem,
 660                  rank,
 661                  size,
 662                  server_name,
 663                  server_port,
 664                  sync_repeat,
 665                  sync_start,
 666                  linkspeed,
 667                  linkdelay,
 668                  dumpfile):
 669     self = Root(full_system = True)
 670     self.testsys = testSystem
 671
 672     self.etherlink = DistEtherLink(speed = linkspeed,
 673                                    delay = linkdelay,
 674                                    dist_rank = rank,
 675                                    dist_size = size,
 676                                    server_name = server_name,
 677                                    server_port = server_port,
 678                                    sync_start = sync_start,
 679                                    sync_repeat = sync_repeat)
 680
 681     if hasattr(testSystem, 'realview'):
 682         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 683     elif hasattr(testSystem, 'tsunami'):
 684         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 685     else:
 686         fatal("Don't know how to connect DistEtherLink to this system")
 687
 688     if dumpfile:
 689         self.etherdump = EtherDump(file=dumpfile)
 690         self.etherlink.dump = Parent.etherdump
 691
 692     return self