1 # Copyright (c) 2006-2008 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 from m5
import makeList
31 from m5
.objects
import *
32 from Benchmarks
import *
34 class CowIdeDisk(IdeDisk
):
35 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
38 def childImage(self
, ci
):
39 self
.image
.child
.image_file
= ci
42 badaddr_responder
= BadAddr()
43 default
= Self
.badaddr_responder
.pio
46 def makeLinuxAlphaSystem(mem_mode
, mdesc
= None):
47 class BaseTsunami(Tsunami
):
48 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
49 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
50 pci_func
=0, pci_dev
=0, pci_bus
=0)
52 self
= LinuxAlphaSystem()
56 self
.readfile
= mdesc
.script()
57 self
.iobus
= Bus(bus_id
=0)
58 self
.membus
= MemBus(bus_id
=1)
59 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
60 self
.physmem
= PhysicalMemory(range = AddrRange(mdesc
.mem()))
61 self
.bridge
.side_a
= self
.iobus
.port
62 self
.bridge
.side_b
= self
.membus
.port
63 self
.physmem
.port
= self
.membus
.port
64 self
.disk0
= CowIdeDisk(driveID
='master')
65 self
.disk2
= CowIdeDisk(driveID
='master')
66 self
.disk0
.childImage(mdesc
.disk())
67 self
.disk2
.childImage(disk('linux-bigswap2.img'))
68 self
.tsunami
= BaseTsunami()
69 self
.tsunami
.attachIO(self
.iobus
)
70 self
.tsunami
.ide
.pio
= self
.iobus
.port
71 self
.tsunami
.ethernet
.pio
= self
.iobus
.port
72 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
74 self
.intrctrl
= IntrControl()
75 self
.mem_mode
= mem_mode
76 self
.terminal
= Terminal()
77 self
.kernel
= binary('vmlinux')
78 self
.pal
= binary('ts_osfpal')
79 self
.console
= binary('console')
80 self
.boot_osflags
= 'root=/dev/hda1 console=ttyS0'
84 def makeSparcSystem(mem_mode
, mdesc
= None):
85 class CowMmDisk(MmDisk
):
86 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
89 def childImage(self
, ci
):
90 self
.image
.child
.image_file
= ci
96 self
.readfile
= mdesc
.script()
97 self
.iobus
= Bus(bus_id
=0)
98 self
.membus
= MemBus(bus_id
=1)
99 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
101 self
.t1000
.attachOnChipIO(self
.membus
)
102 self
.t1000
.attachIO(self
.iobus
)
103 self
.physmem
= PhysicalMemory(range = AddrRange(Addr('1MB'), size
= '64MB'), zero
= True)
104 self
.physmem2
= PhysicalMemory(range = AddrRange(Addr('2GB'), size
='256MB'), zero
= True)
105 self
.bridge
.side_a
= self
.iobus
.port
106 self
.bridge
.side_b
= self
.membus
.port
107 self
.physmem
.port
= self
.membus
.port
108 self
.physmem2
.port
= self
.membus
.port
109 self
.rom
.port
= self
.membus
.port
110 self
.nvram
.port
= self
.membus
.port
111 self
.hypervisor_desc
.port
= self
.membus
.port
112 self
.partition_desc
.port
= self
.membus
.port
113 self
.intrctrl
= IntrControl()
114 self
.disk0
= CowMmDisk()
115 self
.disk0
.childImage(disk('disk.s10hw2'))
116 self
.disk0
.pio
= self
.iobus
.port
117 self
.reset_bin
= binary('reset_new.bin')
118 self
.hypervisor_bin
= binary('q_new.bin')
119 self
.openboot_bin
= binary('openboot_new.bin')
120 self
.nvram_bin
= binary('nvram1')
121 self
.hypervisor_desc_bin
= binary('1up-hv.bin')
122 self
.partition_desc_bin
= binary('1up-md.bin')
126 def makeLinuxMipsSystem(mem_mode
, mdesc
= None):
127 class BaseMalta(Malta
):
128 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
129 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
130 pci_func
=0, pci_dev
=0, pci_bus
=0)
132 self
= LinuxMipsSystem()
136 self
.readfile
= mdesc
.script()
137 self
.iobus
= Bus(bus_id
=0)
138 self
.membus
= MemBus(bus_id
=1)
139 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
140 self
.physmem
= PhysicalMemory(range = AddrRange('1GB'))
141 self
.bridge
.side_a
= self
.iobus
.port
142 self
.bridge
.side_b
= self
.membus
.port
143 self
.physmem
.port
= self
.membus
.port
144 self
.disk0
= CowIdeDisk(driveID
='master')
145 self
.disk2
= CowIdeDisk(driveID
='master')
146 self
.disk0
.childImage(mdesc
.disk())
147 self
.disk2
.childImage(disk('linux-bigswap2.img'))
148 self
.malta
= BaseMalta()
149 self
.malta
.attachIO(self
.iobus
)
150 self
.malta
.ide
.pio
= self
.iobus
.port
151 self
.malta
.ethernet
.pio
= self
.iobus
.port
152 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
154 self
.intrctrl
= IntrControl()
155 self
.mem_mode
= mem_mode
156 self
.terminal
= Terminal()
157 self
.kernel
= binary('mips/vmlinux')
158 self
.console
= binary('mips/console')
159 self
.boot_osflags
= 'root=/dev/hda1 console=ttyS0'
163 def x86IOAddress(port
):
164 IO_address_space_base
= 0x8000000000000000
165 return IO_address_space_base
+ port
;
167 def makeX86System(mem_mode
, mdesc
= None, self
= None):
174 mdesc
.diskname
= 'x86root.img'
175 self
.readfile
= mdesc
.script()
178 self
.membus
= MemBus(bus_id
=1)
179 self
.physmem
= PhysicalMemory(range = AddrRange(mdesc
.mem()))
180 self
.physmem
.port
= self
.membus
.port
183 self
.iobus
= Bus(bus_id
=0)
184 self
.bridge
= Bridge(delay
='50ns', nack_delay
='4ns')
185 self
.bridge
.side_a
= self
.iobus
.port
186 self
.bridge
.side_b
= self
.membus
.port
190 self
.pc
.attachIO(self
.iobus
)
192 self
.intrctrl
= IntrControl()
195 disk0
= CowIdeDisk(driveID
='master')
196 disk2
= CowIdeDisk(driveID
='master')
197 disk0
.childImage(mdesc
.disk())
198 disk2
.childImage(disk('linux-bigswap2.img'))
199 self
.pc
.south_bridge
.ide
.disks
= [disk0
, disk2
]
201 # Add in a Bios information structure.
202 structures
= [X86SMBiosBiosInformation()]
203 self
.smbios_table
.structures
= structures
205 # Set up the Intel MP table
206 bp
= X86IntelMPProcessor(
208 local_apic_version
= 0x14,
211 self
.intel_mp_table
.add_entry(bp
)
212 io_apic
= X86IntelMPIOAPIC(
216 address
= 0xfec00000)
217 self
.intel_mp_table
.add_entry(io_apic
)
218 isa_bus
= X86IntelMPBus(bus_id
= 0, bus_type
='ISA')
219 self
.intel_mp_table
.add_entry(isa_bus
)
220 pci_bus
= X86IntelMPBus(bus_id
= 1, bus_type
='PCI')
221 self
.intel_mp_table
.add_entry(pci_bus
)
222 connect_busses
= X86IntelMPBusHierarchy(bus_id
=0,
223 subtractive_decode
=True, parent_bus
=1)
224 self
.intel_mp_table
.add_entry(connect_busses
)
225 pci_dev4_inta
= X86IntelMPIOIntAssignment(
226 interrupt_type
= 'INT',
227 polarity
= 'ConformPolarity',
228 trigger
= 'ConformTrigger',
230 source_bus_irq
= 0 + (4 << 2),
231 dest_io_apic_id
= io_apic
.id,
232 dest_io_apic_intin
= 16)
233 self
.intel_mp_table
.add_entry(pci_dev4_inta
);
234 assign_8259_0_to_apic
= X86IntelMPIOIntAssignment(
235 interrupt_type
= 'ExtInt',
236 polarity
= 'ConformPolarity',
237 trigger
= 'ConformTrigger',
240 dest_io_apic_id
= io_apic
.id,
241 dest_io_apic_intin
= 0)
242 self
.intel_mp_table
.add_entry(assign_8259_0_to_apic
)
243 assign_0_to_apic
= X86IntelMPIOIntAssignment(
244 interrupt_type
= 'INT',
245 polarity
= 'ConformPolarity',
246 trigger
= 'ConformTrigger',
249 dest_io_apic_id
= io_apic
.id,
250 dest_io_apic_intin
= 2)
251 self
.intel_mp_table
.add_entry(assign_0_to_apic
)
252 assign_8259_1_to_apic
= X86IntelMPIOIntAssignment(
253 interrupt_type
= 'ExtInt',
254 polarity
= 'ConformPolarity',
255 trigger
= 'ConformTrigger',
258 dest_io_apic_id
= io_apic
.id,
259 dest_io_apic_intin
= 0)
260 self
.intel_mp_table
.add_entry(assign_8259_1_to_apic
)
261 assign_1_to_apic
= X86IntelMPIOIntAssignment(
262 interrupt_type
= 'INT',
263 polarity
= 'ConformPolarity',
264 trigger
= 'ConformTrigger',
267 dest_io_apic_id
= io_apic
.id,
268 dest_io_apic_intin
= 1)
269 self
.intel_mp_table
.add_entry(assign_1_to_apic
)
270 assign_8259_4_to_apic
= X86IntelMPIOIntAssignment(
271 interrupt_type
= 'ExtInt',
272 polarity
= 'ConformPolarity',
273 trigger
= 'ConformTrigger',
276 dest_io_apic_id
= io_apic
.id,
277 dest_io_apic_intin
= 0)
278 self
.intel_mp_table
.add_entry(assign_8259_4_to_apic
)
279 assign_4_to_apic
= X86IntelMPIOIntAssignment(
280 interrupt_type
= 'INT',
281 polarity
= 'ConformPolarity',
282 trigger
= 'ConformTrigger',
285 dest_io_apic_id
= io_apic
.id,
286 dest_io_apic_intin
= 4)
287 self
.intel_mp_table
.add_entry(assign_4_to_apic
)
288 assign_8259_12_to_apic
= X86IntelMPIOIntAssignment(
289 interrupt_type
= 'ExtInt',
290 polarity
= 'ConformPolarity',
291 trigger
= 'ConformTrigger',
294 dest_io_apic_id
= io_apic
.id,
295 dest_io_apic_intin
= 0)
296 self
.intel_mp_table
.add_entry(assign_8259_12_to_apic
)
297 assign_12_to_apic
= X86IntelMPIOIntAssignment(
298 interrupt_type
= 'INT',
299 polarity
= 'ConformPolarity',
300 trigger
= 'ConformTrigger',
303 dest_io_apic_id
= io_apic
.id,
304 dest_io_apic_intin
= 12)
305 self
.intel_mp_table
.add_entry(assign_12_to_apic
)
306 assign_8259_14_to_apic
= X86IntelMPIOIntAssignment(
307 interrupt_type
= 'ExtInt',
308 polarity
= 'ConformPolarity',
309 trigger
= 'ConformTrigger',
312 dest_io_apic_id
= io_apic
.id,
313 dest_io_apic_intin
= 0)
314 self
.intel_mp_table
.add_entry(assign_8259_14_to_apic
)
315 assign_14_to_apic
= X86IntelMPIOIntAssignment(
316 interrupt_type
= 'INT',
317 polarity
= 'ConformPolarity',
318 trigger
= 'ConformTrigger',
321 dest_io_apic_id
= io_apic
.id,
322 dest_io_apic_intin
= 14)
323 self
.intel_mp_table
.add_entry(assign_14_to_apic
)
326 def makeLinuxX86System(mem_mode
, mdesc
= None):
327 self
= LinuxX86System()
329 # Build up a generic x86 system and then specialize it for Linux
330 makeX86System(mem_mode
, mdesc
, self
)
332 # We assume below that there's at least 1MB of memory. We'll require 2
333 # just to avoid corner cases.
334 assert(self
.physmem
.range.second
>= 0x200000)
336 # Mark the first megabyte of memory as reserved
337 self
.e820_table
.entries
.append(X86E820Entry(
342 # Mark the rest as available
343 self
.e820_table
.entries
.append(X86E820Entry(
345 size
= '%dB' % (self
.physmem
.range.second
- 0x100000 + 1),
349 self
.boot_osflags
= 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
354 def makeDualRoot(testSystem
, driveSystem
, dumpfile
):
356 self
.testsys
= testSystem
357 self
.drivesys
= driveSystem
358 self
.etherlink
= EtherLink()
359 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
360 self
.etherlink
.int1
= Parent
.drivesys
.tsunami
.ethernet
.interface
363 self
.etherdump
= EtherDump(file=dumpfile
)
364 self
.etherlink
.dump
= Parent
.etherdump
368 def setMipsOptions(TestCPUClass
):
370 TestCPUClass
.CoreParams
.CP0_PRId_CompanyOptions
= 0
371 TestCPUClass
.CoreParams
.CP0_PRId_CompanyID
= 1
372 TestCPUClass
.CoreParams
.CP0_PRId_ProcessorID
= 147
373 TestCPUClass
.CoreParams
.CP0_PRId_Revision
= 0
375 #CP0 Interrupt Control
376 TestCPUClass
.CoreParams
.CP0_IntCtl_IPTI
= 7
377 TestCPUClass
.CoreParams
.CP0_IntCtl_IPPCI
= 7
380 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
381 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
382 TestCPUClass
.CoreParams
.CP0_Config_BE
= 0 # Little Endian
383 TestCPUClass
.CoreParams
.CP0_Config_AR
= 1 # Architecture Revision 2
384 TestCPUClass
.CoreParams
.CP0_Config_AT
= 0 # MIPS32
385 TestCPUClass
.CoreParams
.CP0_Config_MT
= 1 # TLB MMU
386 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
389 TestCPUClass
.CoreParams
.CP0_Config1_M
= 1 # Config2 Implemented
390 TestCPUClass
.CoreParams
.CP0_Config1_MMU
= 63 # TLB Size
391 # ***VERY IMPORTANT***
392 # Remember to modify CP0_Config1 according to cache specs
393 # Examine file ../common/Cache.py
394 TestCPUClass
.CoreParams
.CP0_Config1_IS
= 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
395 TestCPUClass
.CoreParams
.CP0_Config1_IL
= 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
396 TestCPUClass
.CoreParams
.CP0_Config1_IA
= 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
397 TestCPUClass
.CoreParams
.CP0_Config1_DS
= 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
398 TestCPUClass
.CoreParams
.CP0_Config1_DL
= 5 # D-Cache Line Size, default is 64, i.e., 5
399 TestCPUClass
.CoreParams
.CP0_Config1_DA
= 1 # D-Cache Associativity, default is 2, i.e. 1
400 TestCPUClass
.CoreParams
.CP0_Config1_C2
= 0 # Coprocessor 2 not implemented(?)
401 TestCPUClass
.CoreParams
.CP0_Config1_MD
= 0 # MDMX ASE not implemented in Mips32
402 TestCPUClass
.CoreParams
.CP0_Config1_PC
= 1 # Performance Counters Implemented
403 TestCPUClass
.CoreParams
.CP0_Config1_WR
= 0 # Watch Registers Implemented
404 TestCPUClass
.CoreParams
.CP0_Config1_CA
= 0 # Mips16e NOT implemented
405 TestCPUClass
.CoreParams
.CP0_Config1_EP
= 0 # EJTag Not Implemented
406 TestCPUClass
.CoreParams
.CP0_Config1_FP
= 0 # FPU Implemented
409 TestCPUClass
.CoreParams
.CP0_Config2_M
= 1 # Config3 Implemented
410 TestCPUClass
.CoreParams
.CP0_Config2_TU
= 0 # Tertiary Cache Control
411 TestCPUClass
.CoreParams
.CP0_Config2_TS
= 0 # Tertiary Cache Sets Per Way
412 TestCPUClass
.CoreParams
.CP0_Config2_TL
= 0 # Tertiary Cache Line Size
413 TestCPUClass
.CoreParams
.CP0_Config2_TA
= 0 # Tertiary Cache Associativity
414 TestCPUClass
.CoreParams
.CP0_Config2_SU
= 0 # Secondary Cache Control
415 TestCPUClass
.CoreParams
.CP0_Config2_SS
= 0 # Secondary Cache Sets Per Way
416 TestCPUClass
.CoreParams
.CP0_Config2_SL
= 0 # Secondary Cache Line Size
417 TestCPUClass
.CoreParams
.CP0_Config2_SA
= 0 # Secondary Cache Associativity
421 TestCPUClass
.CoreParams
.CP0_Config3_M
= 0 # Config4 Not Implemented
422 TestCPUClass
.CoreParams
.CP0_Config3_DSPP
= 1 # DSP ASE Present
423 TestCPUClass
.CoreParams
.CP0_Config3_LPA
= 0 # Large Physical Addresses Not supported in Mips32
424 TestCPUClass
.CoreParams
.CP0_Config3_VEIC
= 0 # EIC Supported
425 TestCPUClass
.CoreParams
.CP0_Config3_VInt
= 0 # Vectored Interrupts Implemented
426 TestCPUClass
.CoreParams
.CP0_Config3_SP
= 0 # Small Pages Supported (PageGrain reg. exists)
427 TestCPUClass
.CoreParams
.CP0_Config3_MT
= 0 # MT Not present
428 TestCPUClass
.CoreParams
.CP0_Config3_SM
= 0 # SmartMIPS ASE Not implemented
429 TestCPUClass
.CoreParams
.CP0_Config3_TL
= 0 # TraceLogic Not implemented
432 TestCPUClass
.CoreParams
.CP0_SrsCtl_HSS
= 3 # Four shadow register sets implemented
435 #TestCPUClass.CoreParams.tlb = TLB()
436 #TestCPUClass.CoreParams.UnifiedTLB = 1