configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Kevin Lim
  41
  42 from m5.objects import *
  43 from Benchmarks import *
  44 from m5.util import convert
  45
  46 class CowIdeDisk(IdeDisk):
  47     image = CowDiskImage(child=RawDiskImage(read_only=True),
  48                          read_only=False)
  49
  50     def childImage(self, ci):
  51         self.image.child.image_file = ci
  52
  53 class MemBus(CoherentBus):
  54     badaddr_responder = BadAddr()
  55     default = Self.badaddr_responder.pio
  56
  57
  58 def makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None):
  59     IO_address_space_base = 0x80000000000
  60     class BaseTsunami(Tsunami):
  61         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  62         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  63                             pci_func=0, pci_dev=0, pci_bus=0)
  64
  65     self = LinuxAlphaSystem()
  66     if not mdesc:
  67         # generic system
  68         mdesc = SysConfig()
  69     self.readfile = mdesc.script()
  70     self.iobus = NoncoherentBus()
  71     self.membus = MemBus()
  72     # By default the bridge responds to all addresses above the I/O
  73     # base address (including the PCI config space)
  74     self.bridge = Bridge(delay='50ns',
  75                          ranges = [AddrRange(IO_address_space_base, Addr.max)])
  76     self.physmem = MemClass(range = AddrRange(mdesc.mem()))
  77     self.mem_ranges = [self.physmem.range]
  78     self.bridge.master = self.iobus.slave
  79     self.bridge.slave = self.membus.master
  80     self.physmem.port = self.membus.master
  81     self.disk0 = CowIdeDisk(driveID='master')
  82     self.disk2 = CowIdeDisk(driveID='master')
  83     self.disk0.childImage(mdesc.disk())
  84     self.disk2.childImage(disk('linux-bigswap2.img'))
  85     self.tsunami = BaseTsunami()
  86     self.tsunami.attachIO(self.iobus)
  87     self.tsunami.ide.pio = self.iobus.master
  88     self.tsunami.ide.config = self.iobus.master
  89     self.tsunami.ide.dma = self.iobus.slave
  90     self.tsunami.ethernet.pio = self.iobus.master
  91     self.tsunami.ethernet.config = self.iobus.master
  92     self.tsunami.ethernet.dma = self.iobus.slave
  93     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
  94                                                read_only = True))
  95     self.intrctrl = IntrControl()
  96     self.mem_mode = mem_mode
  97     self.terminal = Terminal()
  98     self.kernel = binary('vmlinux')
  99     self.pal = binary('ts_osfpal')
 100     self.console = binary('console')
 101     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 102
 103     self.system_port = self.membus.slave
 104
 105     return self
 106
 107 def makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None):
 108     class BaseTsunami(Tsunami):
 109         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 110         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 111                             pci_func=0, pci_dev=0, pci_bus=0)
 112
 113     physmem = MemClass(range = AddrRange(mdesc.mem()))
 114     self = LinuxAlphaSystem(physmem = physmem)
 115     self.mem_ranges = [self.physmem.range]
 116     if not mdesc:
 117         # generic system
 118         mdesc = SysConfig()
 119     self.readfile = mdesc.script()
 120
 121     # Create pio bus to connect all device pio ports to rubymem's pio port
 122     self.piobus = NoncoherentBus()
 123
 124     #
 125     # Pio functional accesses from devices need direct access to memory
 126     # RubyPort currently does support functional accesses.  Therefore provide
 127     # the piobus a direct connection to physical memory
 128     #
 129     self.piobus.master = physmem.port
 130
 131     self.disk0 = CowIdeDisk(driveID='master')
 132     self.disk2 = CowIdeDisk(driveID='master')
 133     self.disk0.childImage(mdesc.disk())
 134     self.disk2.childImage(disk('linux-bigswap2.img'))
 135     self.tsunami = BaseTsunami()
 136     self.tsunami.attachIO(self.piobus)
 137     self.tsunami.ide.pio = self.piobus.master
 138     self.tsunami.ide.config = self.piobus.master
 139     self.tsunami.ethernet.pio = self.piobus.master
 140     self.tsunami.ethernet.config = self.piobus.master
 141
 142     #
 143     # Store the dma devices for later connection to dma ruby ports.
 144     # Append an underscore to dma_devices to avoid the SimObjectVector check.
 145     #
 146     self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
 147
 148     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 149                                                read_only = True))
 150     self.intrctrl = IntrControl()
 151     self.mem_mode = mem_mode
 152     self.terminal = Terminal()
 153     self.kernel = binary('vmlinux')
 154     self.pal = binary('ts_osfpal')
 155     self.console = binary('console')
 156     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 157
 158     return self
 159
 160 def makeSparcSystem(mem_mode, MemClass, mdesc = None):
 161     # Constants from iob.cc and uart8250.cc
 162     iob_man_addr = 0x9800000000
 163     uart_pio_size = 8
 164
 165     class CowMmDisk(MmDisk):
 166         image = CowDiskImage(child=RawDiskImage(read_only=True),
 167                              read_only=False)
 168
 169         def childImage(self, ci):
 170             self.image.child.image_file = ci
 171
 172     self = SparcSystem()
 173     if not mdesc:
 174         # generic system
 175         mdesc = SysConfig()
 176     self.readfile = mdesc.script()
 177     self.iobus = NoncoherentBus()
 178     self.membus = MemBus()
 179     self.bridge = Bridge(delay='50ns')
 180     self.t1000 = T1000()
 181     self.t1000.attachOnChipIO(self.membus)
 182     self.t1000.attachIO(self.iobus)
 183     self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'))
 184     self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'))
 185     self.mem_ranges = [self.physmem.range, self.physmem2.range]
 186     self.bridge.master = self.iobus.slave
 187     self.bridge.slave = self.membus.master
 188     self.physmem.port = self.membus.master
 189     self.physmem2.port = self.membus.master
 190     self.rom.port = self.membus.master
 191     self.nvram.port = self.membus.master
 192     self.hypervisor_desc.port = self.membus.master
 193     self.partition_desc.port = self.membus.master
 194     self.intrctrl = IntrControl()
 195     self.disk0 = CowMmDisk()
 196     self.disk0.childImage(disk('disk.s10hw2'))
 197     self.disk0.pio = self.iobus.master
 198
 199     # The puart0 and hvuart are placed on the IO bus, so create ranges
 200     # for them. The remaining IO range is rather fragmented, so poke
 201     # holes for the iob and partition descriptors etc.
 202     self.bridge.ranges = \
 203         [
 204         AddrRange(self.t1000.puart0.pio_addr,
 205                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 206         AddrRange(self.disk0.pio_addr,
 207                   self.t1000.fake_jbi.pio_addr +
 208                   self.t1000.fake_jbi.pio_size - 1),
 209         AddrRange(self.t1000.fake_clk.pio_addr,
 210                   iob_man_addr - 1),
 211         AddrRange(self.t1000.fake_l2_1.pio_addr,
 212                   self.t1000.fake_ssi.pio_addr +
 213                   self.t1000.fake_ssi.pio_size - 1),
 214         AddrRange(self.t1000.hvuart.pio_addr,
 215                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 216         ]
 217     self.reset_bin = binary('reset_new.bin')
 218     self.hypervisor_bin = binary('q_new.bin')
 219     self.openboot_bin = binary('openboot_new.bin')
 220     self.nvram_bin = binary('nvram1')
 221     self.hypervisor_desc_bin = binary('1up-hv.bin')
 222     self.partition_desc_bin = binary('1up-md.bin')
 223
 224     self.system_port = self.membus.slave
 225
 226     return self
 227
 228 def makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None,
 229                   dtb_filename = None, bare_metal=False):
 230     assert machine_type
 231
 232     if bare_metal:
 233         self = ArmSystem()
 234     else:
 235         self = LinuxArmSystem()
 236
 237     if not mdesc:
 238         # generic system
 239         mdesc = SysConfig()
 240
 241     self.readfile = mdesc.script()
 242     self.iobus = NoncoherentBus()
 243     self.membus = MemBus()
 244     self.membus.badaddr_responder.warn_access = "warn"
 245     self.bridge = Bridge(delay='50ns')
 246     self.bridge.master = self.iobus.slave
 247     self.bridge.slave = self.membus.master
 248
 249     self.mem_mode = mem_mode
 250
 251     if machine_type == "RealView_PBX":
 252         self.realview = RealViewPBX()
 253     elif machine_type == "RealView_EB":
 254         self.realview = RealViewEB()
 255     elif machine_type == "VExpress_ELT":
 256         self.realview = VExpress_ELT()
 257     elif machine_type == "VExpress_EMM":
 258         self.realview = VExpress_EMM()
 259         self.load_addr_mask = 0xffffffff
 260     else:
 261         print "Unknown Machine Type"
 262         sys.exit(1)
 263
 264     self.cf0 = CowIdeDisk(driveID='master')
 265     self.cf0.childImage(mdesc.disk())
 266     # default to an IDE controller rather than a CF one
 267     # assuming we've got one
 268     try:
 269         self.realview.ide.disks = [self.cf0]
 270     except:
 271         self.realview.cf_ctrl.disks = [self.cf0]
 272
 273     if bare_metal:
 274         # EOT character on UART will end the simulation
 275         self.realview.uart.end_on_eot = True
 276         self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())))
 277         self.mem_ranges = [self.physmem.range]
 278     else:
 279         self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
 280         if dtb_filename is not None:
 281             self.dtb_filename = dtb_filename
 282         self.machine_type = machine_type
 283         if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
 284             print "The currently selected ARM platforms doesn't support"
 285             print " the amount of DRAM you've selected. Please try"
 286             print " another platform"
 287             sys.exit(1)
 288
 289         boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
 290                      'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
 291
 292         self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr,
 293                                                   size = mdesc.mem()),
 294                                 conf_table_reported = True)
 295         self.mem_ranges = [self.physmem.range]
 296         self.realview.setupBootLoader(self.membus, self, binary)
 297         self.gic_cpu_addr = self.realview.gic.cpu_addr
 298         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 299
 300         if mdesc.disk().lower().count('android'):
 301             boot_flags += " init=/init "
 302         self.boot_osflags = boot_flags
 303
 304     self.physmem.port = self.membus.master
 305     self.realview.attachOnChipIO(self.membus, self.bridge)
 306     self.realview.attachIO(self.iobus)
 307     self.intrctrl = IntrControl()
 308     self.terminal = Terminal()
 309     self.vncserver = VncServer()
 310
 311     self.system_port = self.membus.slave
 312
 313     return self
 314
 315
 316 def makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None):
 317     class BaseMalta(Malta):
 318         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 319         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 320                             pci_func=0, pci_dev=0, pci_bus=0)
 321
 322     self = LinuxMipsSystem()
 323     if not mdesc:
 324         # generic system
 325         mdesc = SysConfig()
 326     self.readfile = mdesc.script()
 327     self.iobus = NoncoherentBus()
 328     self.membus = MemBus()
 329     self.bridge = Bridge(delay='50ns')
 330     self.physmem = MemClass(range = AddrRange('1GB'))
 331     self.mem_ranges = [self.physmem.range]
 332     self.bridge.master = self.iobus.slave
 333     self.bridge.slave = self.membus.master
 334     self.physmem.port = self.membus.master
 335     self.disk0 = CowIdeDisk(driveID='master')
 336     self.disk2 = CowIdeDisk(driveID='master')
 337     self.disk0.childImage(mdesc.disk())
 338     self.disk2.childImage(disk('linux-bigswap2.img'))
 339     self.malta = BaseMalta()
 340     self.malta.attachIO(self.iobus)
 341     self.malta.ide.pio = self.iobus.master
 342     self.malta.ide.config = self.iobus.master
 343     self.malta.ide.dma = self.iobus.slave
 344     self.malta.ethernet.pio = self.iobus.master
 345     self.malta.ethernet.config = self.iobus.master
 346     self.malta.ethernet.dma = self.iobus.slave
 347     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 348                                                read_only = True))
 349     self.intrctrl = IntrControl()
 350     self.mem_mode = mem_mode
 351     self.terminal = Terminal()
 352     self.kernel = binary('mips/vmlinux')
 353     self.console = binary('mips/console')
 354     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 355
 356     self.system_port = self.membus.slave
 357
 358     return self
 359
 360 def x86IOAddress(port):
 361     IO_address_space_base = 0x8000000000000000
 362     return IO_address_space_base + port
 363
 364 def connectX86ClassicSystem(x86_sys, numCPUs):
 365     # Constants similar to x86_traits.hh
 366     IO_address_space_base = 0x8000000000000000
 367     pci_config_address_space_base = 0xc000000000000000
 368     interrupts_address_space_base = 0xa000000000000000
 369     APIC_range_size = 1 << 12;
 370
 371     x86_sys.membus = MemBus()
 372     x86_sys.physmem.port = x86_sys.membus.master
 373
 374     # North Bridge
 375     x86_sys.iobus = NoncoherentBus()
 376     x86_sys.bridge = Bridge(delay='50ns')
 377     x86_sys.bridge.master = x86_sys.iobus.slave
 378     x86_sys.bridge.slave = x86_sys.membus.master
 379     # Allow the bridge to pass through the IO APIC (two pages),
 380     # everything in the IO address range up to the local APIC, and
 381     # then the entire PCI address space and beyond
 382     x86_sys.bridge.ranges = \
 383         [
 384         AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
 385                   x86_sys.pc.south_bridge.io_apic.pio_addr +
 386                   APIC_range_size - 1),
 387         AddrRange(IO_address_space_base,
 388                   interrupts_address_space_base - 1),
 389         AddrRange(pci_config_address_space_base,
 390                   Addr.max)
 391         ]
 392
 393     # Create a bridge from the IO bus to the memory bus to allow access to
 394     # the local APIC (two pages)
 395     x86_sys.apicbridge = Bridge(delay='50ns')
 396     x86_sys.apicbridge.slave = x86_sys.iobus.master
 397     x86_sys.apicbridge.master = x86_sys.membus.slave
 398     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 399                                            interrupts_address_space_base +
 400                                            numCPUs * APIC_range_size
 401                                            - 1)]
 402
 403     # connect the io bus
 404     x86_sys.pc.attachIO(x86_sys.iobus)
 405
 406     x86_sys.system_port = x86_sys.membus.slave
 407
 408 def connectX86RubySystem(x86_sys):
 409     # North Bridge
 410     x86_sys.piobus = NoncoherentBus()
 411
 412     #
 413     # Pio functional accesses from devices need direct access to memory
 414     # RubyPort currently does support functional accesses.  Therefore provide
 415     # the piobus a direct connection to physical memory
 416     #
 417     x86_sys.piobus.master = x86_sys.physmem.port
 418     # add the ide to the list of dma devices that later need to attach to
 419     # dma controllers
 420     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 421     x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
 422
 423
 424 def makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None,
 425                   Ruby = False):
 426     if self == None:
 427         self = X86System()
 428
 429     if not mdesc:
 430         # generic system
 431         mdesc = SysConfig()
 432     self.readfile = mdesc.script()
 433
 434     self.mem_mode = mem_mode
 435
 436     # Physical memory
 437     self.physmem = MemClass(range = AddrRange(mdesc.mem()))
 438     self.mem_ranges = [self.physmem.range]
 439
 440     # Platform
 441     self.pc = Pc()
 442
 443     # Create and connect the busses required by each memory system
 444     if Ruby:
 445         connectX86RubySystem(self)
 446     else:
 447         connectX86ClassicSystem(self, numCPUs)
 448
 449     self.intrctrl = IntrControl()
 450
 451     # Disks
 452     disk0 = CowIdeDisk(driveID='master')
 453     disk2 = CowIdeDisk(driveID='master')
 454     disk0.childImage(mdesc.disk())
 455     disk2.childImage(disk('linux-bigswap2.img'))
 456     self.pc.south_bridge.ide.disks = [disk0, disk2]
 457
 458     # Add in a Bios information structure.
 459     structures = [X86SMBiosBiosInformation()]
 460     self.smbios_table.structures = structures
 461
 462     # Set up the Intel MP table
 463     base_entries = []
 464     ext_entries = []
 465     for i in xrange(numCPUs):
 466         bp = X86IntelMPProcessor(
 467                 local_apic_id = i,
 468                 local_apic_version = 0x14,
 469                 enable = True,
 470                 bootstrap = (i == 0))
 471         base_entries.append(bp)
 472     io_apic = X86IntelMPIOAPIC(
 473             id = numCPUs,
 474             version = 0x11,
 475             enable = True,
 476             address = 0xfec00000)
 477     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 478     base_entries.append(io_apic)
 479     isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
 480     base_entries.append(isa_bus)
 481     pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
 482     base_entries.append(pci_bus)
 483     connect_busses = X86IntelMPBusHierarchy(bus_id=0,
 484             subtractive_decode=True, parent_bus=1)
 485     ext_entries.append(connect_busses)
 486     pci_dev4_inta = X86IntelMPIOIntAssignment(
 487             interrupt_type = 'INT',
 488             polarity = 'ConformPolarity',
 489             trigger = 'ConformTrigger',
 490             source_bus_id = 1,
 491             source_bus_irq = 0 + (4 << 2),
 492             dest_io_apic_id = io_apic.id,
 493             dest_io_apic_intin = 16)
 494     base_entries.append(pci_dev4_inta)
 495     def assignISAInt(irq, apicPin):
 496         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 497                 interrupt_type = 'ExtInt',
 498                 polarity = 'ConformPolarity',
 499                 trigger = 'ConformTrigger',
 500                 source_bus_id = 0,
 501                 source_bus_irq = irq,
 502                 dest_io_apic_id = io_apic.id,
 503                 dest_io_apic_intin = 0)
 504         base_entries.append(assign_8259_to_apic)
 505         assign_to_apic = X86IntelMPIOIntAssignment(
 506                 interrupt_type = 'INT',
 507                 polarity = 'ConformPolarity',
 508                 trigger = 'ConformTrigger',
 509                 source_bus_id = 0,
 510                 source_bus_irq = irq,
 511                 dest_io_apic_id = io_apic.id,
 512                 dest_io_apic_intin = apicPin)
 513         base_entries.append(assign_to_apic)
 514     assignISAInt(0, 2)
 515     assignISAInt(1, 1)
 516     for i in range(3, 15):
 517         assignISAInt(i, i)
 518     self.intel_mp_table.base_entries = base_entries
 519     self.intel_mp_table.ext_entries = ext_entries
 520
 521 def makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None,
 522                        Ruby = False):
 523     self = LinuxX86System()
 524
 525     # Build up the x86 system and then specialize it for Linux
 526     makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby)
 527
 528     # We assume below that there's at least 1MB of memory. We'll require 2
 529     # just to avoid corner cases.
 530     phys_mem_size = sum(map(lambda mem: mem.range.size(),
 531                             self.memories.unproxy(self)))
 532     assert(phys_mem_size >= 0x200000)
 533
 534     self.e820_table.entries = \
 535        [
 536         # Mark the first megabyte of memory as reserved
 537         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 538         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 539         # Mark the rest as available
 540         X86E820Entry(addr = 0x100000,
 541                 size = '%dB' % (phys_mem_size - 0x100000),
 542                 range_type = 1)
 543         ]
 544
 545     # Command line
 546     self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
 547                         'root=/dev/hda1'
 548     return self
 549
 550
 551 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 552     self = Root(full_system = full_system)
 553     self.testsys = testSystem
 554     self.drivesys = driveSystem
 555     self.etherlink = EtherLink()
 556     self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 557     self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 558
 559     if hasattr(testSystem, 'realview'):
 560         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 561         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 562     elif hasattr(testSystem, 'tsunami'):
 563         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 564         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 565     else:
 566         fatal("Don't know how to connect these system together")
 567
 568     if dumpfile:
 569         self.etherdump = EtherDump(file=dumpfile)
 570         self.etherlink.dump = Parent.etherdump
 571
 572     return self