configs/common/MemConfig.py

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  36 # Authors: Andreas Sandberg
  37 #          Andreas Hansson
  38
  39 from __future__ import print_function
  40 from __future__ import absolute_import
  41
  42 import m5.objects
  43 from common import ObjectList
  44 from . import HMC
  45
  46 def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
  47     """
  48     Helper function for creating a single memoy controller from the given
  49     options.  This function is invoked multiple times in config_mem function
  50     to create an array of controllers.
  51     """
  52
  53     import math
  54     intlv_low_bit = int(math.log(intlv_size, 2))
  55
  56     # Use basic hashing for the channel selection, and preferably use
  57     # the lower tag bits from the last level cache. As we do not know
  58     # the details of the caches here, make an educated guess. 4 MByte
  59     # 4-way associative with 64 byte cache lines is 6 offset bits and
  60     # 14 index bits.
  61     xor_low_bit = 20
  62
  63     # Create an instance so we can figure out the address
  64     # mapping and row-buffer size
  65     ctrl = cls()
  66
  67     # Only do this for DRAMs
  68     if issubclass(cls, m5.objects.DRAMCtrl):
  69         # If the channel bits are appearing after the column
  70         # bits, we need to add the appropriate number of bits
  71         # for the row buffer size
  72         if ctrl.addr_mapping.value == 'RoRaBaChCo':
  73             # This computation only really needs to happen
  74             # once, but as we rely on having an instance we
  75             # end up having to repeat it for each and every
  76             # one
  77             rowbuffer_size = ctrl.device_rowbuffer_size.value * \
  78                 ctrl.devices_per_rank.value
  79
  80             intlv_low_bit = int(math.log(rowbuffer_size, 2))
  81
  82     # We got all we need to configure the appropriate address
  83     # range
  84     ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
  85                                       intlvHighBit = \
  86                                           intlv_low_bit + intlv_bits - 1,
  87                                       xorHighBit = \
  88                                           xor_low_bit + intlv_bits - 1,
  89                                       intlvBits = intlv_bits,
  90                                       intlvMatch = i)
  91     return ctrl
  92
  93 def config_mem(options, system):
  94     """
  95     Create the memory controllers based on the options and attach them.
  96
  97     If requested, we make a multi-channel configuration of the
  98     selected memory controller class by creating multiple instances of
  99     the specific class. The individual controllers have their
 100     parameters set such that the address range is interleaved between
 101     them.
 102     """
 103
 104     # Mandatory options
 105     opt_mem_type = options.mem_type
 106     opt_mem_channels = options.mem_channels
 107
 108     # Optional options
 109     opt_tlm_memory = getattr(options, "tlm_memory", None)
 110     opt_external_memory_system = getattr(options, "external_memory_system",
 111                                          None)
 112     opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
 113     opt_mem_ranks = getattr(options, "mem_ranks", None)
 114     opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
 115
 116     if opt_mem_type == "HMC_2500_1x32":
 117         HMChost = HMC.config_hmc_host_ctrl(options, system)
 118         HMC.config_hmc_dev(options, system, HMChost.hmc_host)
 119         subsystem = system.hmc_dev
 120         xbar = system.hmc_dev.xbar
 121     else:
 122         subsystem = system
 123         xbar = system.membus
 124
 125     if opt_tlm_memory:
 126         system.external_memory = m5.objects.ExternalSlave(
 127             port_type="tlm_slave",
 128             port_data=opt_tlm_memory,
 129             port=system.membus.master,
 130             addr_ranges=system.mem_ranges)
 131         system.kernel_addr_check = False
 132         return
 133
 134     if opt_external_memory_system:
 135         subsystem.external_memory = m5.objects.ExternalSlave(
 136             port_type=opt_external_memory_system,
 137             port_data="init_mem0", port=xbar.master,
 138             addr_ranges=system.mem_ranges)
 139         subsystem.kernel_addr_check = False
 140         return
 141
 142     nbr_mem_ctrls = opt_mem_channels
 143     import math
 144     from m5.util import fatal
 145     intlv_bits = int(math.log(nbr_mem_ctrls, 2))
 146     if 2 ** intlv_bits != nbr_mem_ctrls:
 147         fatal("Number of memory channels must be a power of 2")
 148
 149     cls = ObjectList.mem_list.get(opt_mem_type)
 150     mem_ctrls = []
 151
 152     if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory):
 153         fatal("When elastic trace is enabled, configure mem-type as "
 154                 "simple-mem.")
 155
 156     # The default behaviour is to interleave memory channels on 128
 157     # byte granularity, or cache line granularity if larger than 128
 158     # byte. This value is based on the locality seen across a large
 159     # range of workloads.
 160     intlv_size = max(128, system.cache_line_size.value)
 161
 162     # For every range (most systems will only have one), create an
 163     # array of controllers and set their parameters to match their
 164     # address mapping in the case of a DRAM
 165     for r in system.mem_ranges:
 166         for i in range(nbr_mem_ctrls):
 167             mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
 168                                        intlv_size)
 169             # Set the number of ranks based on the command-line
 170             # options if it was explicitly set
 171             if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
 172                 mem_ctrl.ranks_per_channel = opt_mem_ranks
 173
 174             # Enable low-power DRAM states if option is set
 175             if issubclass(cls, m5.objects.DRAMCtrl):
 176                 mem_ctrl.enable_dram_powerdown = opt_dram_powerdown
 177
 178             if opt_elastic_trace_en:
 179                 mem_ctrl.latency = '1ns'
 180                 print("For elastic trace, over-riding Simple Memory "
 181                     "latency to 1ns.")
 182
 183             mem_ctrls.append(mem_ctrl)
 184
 185     subsystem.mem_ctrls = mem_ctrls
 186
 187     # Connect the controllers to the membus
 188     for i in range(len(subsystem.mem_ctrls)):
 189         if opt_mem_type == "HMC_2500_1x32":
 190             subsystem.mem_ctrls[i].port = xbar[i/4].master
 191             # Set memory device size. There is an independent controller for
 192             # each vault. All vaults are same size.
 193             subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size
 194         else:
 195             subsystem.mem_ctrls[i].port = xbar.master