configs/common/MemConfig.py

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  35
  36 from __future__ import print_function
  37 from __future__ import absolute_import
  38
  39 import m5.objects
  40 from common import ObjectList
  41 from common import HMC
  42
  43 def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
  44     """
  45     Helper function for creating a single memoy controller from the given
  46     options.  This function is invoked multiple times in config_mem function
  47     to create an array of controllers.
  48     """
  49
  50     import math
  51     intlv_low_bit = int(math.log(intlv_size, 2))
  52
  53     # Use basic hashing for the channel selection, and preferably use
  54     # the lower tag bits from the last level cache. As we do not know
  55     # the details of the caches here, make an educated guess. 4 MByte
  56     # 4-way associative with 64 byte cache lines is 6 offset bits and
  57     # 14 index bits.
  58     xor_low_bit = 20
  59
  60     # Create an instance so we can figure out the address
  61     # mapping and row-buffer size
  62     ctrl = cls()
  63
  64     # Only do this for DRAMs
  65     if issubclass(cls, m5.objects.DRAMCtrl):
  66         # If the channel bits are appearing after the column
  67         # bits, we need to add the appropriate number of bits
  68         # for the row buffer size
  69         if ctrl.addr_mapping.value == 'RoRaBaChCo':
  70             # This computation only really needs to happen
  71             # once, but as we rely on having an instance we
  72             # end up having to repeat it for each and every
  73             # one
  74             rowbuffer_size = ctrl.device_rowbuffer_size.value * \
  75                 ctrl.devices_per_rank.value
  76
  77             intlv_low_bit = int(math.log(rowbuffer_size, 2))
  78
  79     # We got all we need to configure the appropriate address
  80     # range
  81     ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
  82                                       intlvHighBit = \
  83                                           intlv_low_bit + intlv_bits - 1,
  84                                       xorHighBit = \
  85                                           xor_low_bit + intlv_bits - 1,
  86                                       intlvBits = intlv_bits,
  87                                       intlvMatch = i)
  88     return ctrl
  89
  90 def config_mem(options, system):
  91     """
  92     Create the memory controllers based on the options and attach them.
  93
  94     If requested, we make a multi-channel configuration of the
  95     selected memory controller class by creating multiple instances of
  96     the specific class. The individual controllers have their
  97     parameters set such that the address range is interleaved between
  98     them.
  99     """
 100
 101     # Mandatory options
 102     opt_mem_type = options.mem_type
 103     opt_mem_channels = options.mem_channels
 104
 105     # Optional options
 106     opt_tlm_memory = getattr(options, "tlm_memory", None)
 107     opt_external_memory_system = getattr(options, "external_memory_system",
 108                                          None)
 109     opt_elastic_trace_en = getattr(options, "elastic_trace_en", False)
 110     opt_mem_ranks = getattr(options, "mem_ranks", None)
 111     opt_dram_powerdown = getattr(options, "enable_dram_powerdown", None)
 112     opt_mem_channels_intlv = getattr(options, "mem_channels_intlv", 128)
 113
 114     if opt_mem_type == "HMC_2500_1x32":
 115         HMChost = HMC.config_hmc_host_ctrl(options, system)
 116         HMC.config_hmc_dev(options, system, HMChost.hmc_host)
 117         subsystem = system.hmc_dev
 118         xbar = system.hmc_dev.xbar
 119     else:
 120         subsystem = system
 121         xbar = system.membus
 122
 123     if opt_tlm_memory:
 124         system.external_memory = m5.objects.ExternalSlave(
 125             port_type="tlm_slave",
 126             port_data=opt_tlm_memory,
 127             port=system.membus.master,
 128             addr_ranges=system.mem_ranges)
 129         system.workload.addr_check = False
 130         return
 131
 132     if opt_external_memory_system:
 133         subsystem.external_memory = m5.objects.ExternalSlave(
 134             port_type=opt_external_memory_system,
 135             port_data="init_mem0", port=xbar.master,
 136             addr_ranges=system.mem_ranges)
 137         subsystem.workload.addr_check = False
 138         return
 139
 140     nbr_mem_ctrls = opt_mem_channels
 141     import math
 142     from m5.util import fatal
 143     intlv_bits = int(math.log(nbr_mem_ctrls, 2))
 144     if 2 ** intlv_bits != nbr_mem_ctrls:
 145         fatal("Number of memory channels must be a power of 2")
 146
 147     cls = ObjectList.mem_list.get(opt_mem_type)
 148     mem_ctrls = []
 149
 150     if opt_elastic_trace_en and not issubclass(cls, m5.objects.SimpleMemory):
 151         fatal("When elastic trace is enabled, configure mem-type as "
 152                 "simple-mem.")
 153
 154     # The default behaviour is to interleave memory channels on 128
 155     # byte granularity, or cache line granularity if larger than 128
 156     # byte. This value is based on the locality seen across a large
 157     # range of workloads.
 158     intlv_size = max(opt_mem_channels_intlv, system.cache_line_size.value)
 159
 160     # For every range (most systems will only have one), create an
 161     # array of controllers and set their parameters to match their
 162     # address mapping in the case of a DRAM
 163     for r in system.mem_ranges:
 164         for i in range(nbr_mem_ctrls):
 165             mem_ctrl = create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits,
 166                                        intlv_size)
 167             # Set the number of ranks based on the command-line
 168             # options if it was explicitly set
 169             if issubclass(cls, m5.objects.DRAMCtrl) and opt_mem_ranks:
 170                 mem_ctrl.ranks_per_channel = opt_mem_ranks
 171
 172             # Enable low-power DRAM states if option is set
 173             if issubclass(cls, m5.objects.DRAMCtrl):
 174                 mem_ctrl.enable_dram_powerdown = opt_dram_powerdown
 175
 176             if opt_elastic_trace_en:
 177                 mem_ctrl.latency = '1ns'
 178                 print("For elastic trace, over-riding Simple Memory "
 179                     "latency to 1ns.")
 180
 181             mem_ctrls.append(mem_ctrl)
 182
 183     subsystem.mem_ctrls = mem_ctrls
 184
 185     # Connect the controllers to the membus
 186     for i in range(len(subsystem.mem_ctrls)):
 187         if opt_mem_type == "HMC_2500_1x32":
 188             subsystem.mem_ctrls[i].port = xbar[i/4].master
 189             # Set memory device size. There is an independent controller for
 190             # each vault. All vaults are same size.
 191             subsystem.mem_ctrls[i].device_size = options.hmc_dev_vault_size
 192         else:
 193             subsystem.mem_ctrls[i].port = xbar.master