1 # Copyright (c) 2013, 2017 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
39 from __future__
import print_function
45 from textwrap
import TextWrapper
47 # Dictionary of mapping names of real memory controller models to
51 def is_mem_class(cls
):
52 """Determine if a class is a memory controller that can be instantiated"""
54 # We can't use the normal inspect.isclass because the ParamFactory
55 # and ProxyFactory classes have a tendency to confuse it.
57 return issubclass(cls
, m5
.objects
.AbstractMemory
) and \
63 """Get a memory class from a user provided class name."""
66 mem_class
= _mem_classes
[name
]
69 print("%s is not a valid memory controller." % (name
,))
73 """Print a list of available memory classes."""
75 print("Available memory classes:")
76 doc_wrapper
= TextWrapper(initial_indent
="\t\t", subsequent_indent
="\t\t")
77 for name
, cls
in _mem_classes
.items():
80 # Try to extract the class documentation from the class help
82 doc
= inspect
.getdoc(cls
)
84 for line
in doc_wrapper
.wrap(doc
):
88 """Return a list of valid memory names."""
89 return list(_mem_classes
.keys())
91 # Add all memory controllers in the object hierarchy.
92 for name
, cls
in inspect
.getmembers(m5
.objects
, is_mem_class
):
93 _mem_classes
[name
] = cls
95 def create_mem_ctrl(cls
, r
, i
, nbr_mem_ctrls
, intlv_bits
, intlv_size
):
97 Helper function for creating a single memoy controller from the given
98 options. This function is invoked multiple times in config_mem function
99 to create an array of controllers.
103 intlv_low_bit
= int(math
.log(intlv_size
, 2))
105 # Use basic hashing for the channel selection, and preferably use
106 # the lower tag bits from the last level cache. As we do not know
107 # the details of the caches here, make an educated guess. 4 MByte
108 # 4-way associative with 64 byte cache lines is 6 offset bits and
112 # Create an instance so we can figure out the address
113 # mapping and row-buffer size
116 # Only do this for DRAMs
117 if issubclass(cls
, m5
.objects
.DRAMCtrl
):
118 # Inform each controller how many channels to account
120 ctrl
.channels
= nbr_mem_ctrls
122 # If the channel bits are appearing after the column
123 # bits, we need to add the appropriate number of bits
124 # for the row buffer size
125 if ctrl
.addr_mapping
.value
== 'RoRaBaChCo':
126 # This computation only really needs to happen
127 # once, but as we rely on having an instance we
128 # end up having to repeat it for each and every
130 rowbuffer_size
= ctrl
.device_rowbuffer_size
.value
* \
131 ctrl
.devices_per_rank
.value
133 intlv_low_bit
= int(math
.log(rowbuffer_size
, 2))
135 # We got all we need to configure the appropriate address
137 ctrl
.range = m5
.objects
.AddrRange(r
.start
, size
= r
.size(),
139 intlv_low_bit
+ intlv_bits
- 1,
141 xor_low_bit
+ intlv_bits
- 1,
142 intlvBits
= intlv_bits
,
146 def config_mem(options
, system
):
148 Create the memory controllers based on the options and attach them.
150 If requested, we make a multi-channel configuration of the
151 selected memory controller class by creating multiple instances of
152 the specific class. The individual controllers have their
153 parameters set such that the address range is interleaved between
158 opt_mem_type
= options
.mem_type
159 opt_mem_channels
= options
.mem_channels
162 opt_tlm_memory
= getattr(options
, "tlm_memory", None)
163 opt_external_memory_system
= getattr(options
, "external_memory_system",
165 opt_elastic_trace_en
= getattr(options
, "elastic_trace_en", False)
166 opt_mem_ranks
= getattr(options
, "mem_ranks", None)
168 if opt_mem_type
== "HMC_2500_1x32":
169 HMChost
= HMC
.config_hmc_host_ctrl(options
, system
)
170 HMC
.config_hmc_dev(options
, system
, HMChost
.hmc_host
)
171 subsystem
= system
.hmc_dev
172 xbar
= system
.hmc_dev
.xbar
178 system
.external_memory
= m5
.objects
.ExternalSlave(
179 port_type
="tlm_slave",
180 port_data
=opt_tlm_memory
,
181 port
=system
.membus
.master
,
182 addr_ranges
=system
.mem_ranges
)
183 system
.kernel_addr_check
= False
186 if opt_external_memory_system
:
187 subsystem
.external_memory
= m5
.objects
.ExternalSlave(
188 port_type
=opt_external_memory_system
,
189 port_data
="init_mem0", port
=xbar
.master
,
190 addr_ranges
=system
.mem_ranges
)
191 subsystem
.kernel_addr_check
= False
194 nbr_mem_ctrls
= opt_mem_channels
196 from m5
.util
import fatal
197 intlv_bits
= int(math
.log(nbr_mem_ctrls
, 2))
198 if 2 ** intlv_bits
!= nbr_mem_ctrls
:
199 fatal("Number of memory channels must be a power of 2")
201 cls
= get(opt_mem_type
)
204 if opt_elastic_trace_en
and not issubclass(cls
, m5
.objects
.SimpleMemory
):
205 fatal("When elastic trace is enabled, configure mem-type as "
208 # The default behaviour is to interleave memory channels on 128
209 # byte granularity, or cache line granularity if larger than 128
210 # byte. This value is based on the locality seen across a large
211 # range of workloads.
212 intlv_size
= max(128, system
.cache_line_size
.value
)
214 # For every range (most systems will only have one), create an
215 # array of controllers and set their parameters to match their
216 # address mapping in the case of a DRAM
217 for r
in system
.mem_ranges
:
218 for i
in range(nbr_mem_ctrls
):
219 mem_ctrl
= create_mem_ctrl(cls
, r
, i
, nbr_mem_ctrls
, intlv_bits
,
221 # Set the number of ranks based on the command-line
222 # options if it was explicitly set
223 if issubclass(cls
, m5
.objects
.DRAMCtrl
) and opt_mem_ranks
:
224 mem_ctrl
.ranks_per_channel
= opt_mem_ranks
226 if opt_elastic_trace_en
:
227 mem_ctrl
.latency
= '1ns'
228 print("For elastic trace, over-riding Simple Memory "
231 mem_ctrls
.append(mem_ctrl
)
233 subsystem
.mem_ctrls
= mem_ctrls
235 # Connect the controllers to the membus
236 for i
in range(len(subsystem
.mem_ctrls
)):
237 if opt_mem_type
== "HMC_2500_1x32":
238 subsystem
.mem_ctrls
[i
].port
= xbar
[i
/4].master
239 # Set memory device size. There is an independent controller for
240 # each vault. All vaults are same size.
241 subsystem
.mem_ctrls
[i
].device_size
= options
.hmc_dev_vault_size
243 subsystem
.mem_ctrls
[i
].port
= xbar
.master