1 # Copyright (c) 2013 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
43 from textwrap
import TextWrapper
45 # Dictionary of mapping names of real memory controller models to
49 def is_mem_class(cls
):
50 """Determine if a class is a memory controller that can be instantiated"""
52 # We can't use the normal inspect.isclass because the ParamFactory
53 # and ProxyFactory classes have a tendency to confuse it.
55 return issubclass(cls
, m5
.objects
.AbstractMemory
) and \
61 """Get a memory class from a user provided class name."""
64 mem_class
= _mem_classes
[name
]
67 print "%s is not a valid memory controller." % (name
,)
71 """Print a list of available memory classes."""
73 print "Available memory classes:"
74 doc_wrapper
= TextWrapper(initial_indent
="\t\t", subsequent_indent
="\t\t")
75 for name
, cls
in _mem_classes
.items():
78 # Try to extract the class documentation from the class help
80 doc
= inspect
.getdoc(cls
)
82 for line
in doc_wrapper
.wrap(doc
):
86 """Return a list of valid memory names."""
87 return _mem_classes
.keys()
89 # Add all memory controllers in the object hierarchy.
90 for name
, cls
in inspect
.getmembers(m5
.objects
, is_mem_class
):
91 _mem_classes
[name
] = cls
93 def create_mem_ctrl(cls
, r
, i
, nbr_mem_ctrls
, intlv_bits
, intlv_size
):
95 Helper function for creating a single memoy controller from the given
96 options. This function is invoked multiple times in config_mem function
97 to create an array of controllers.
101 intlv_low_bit
= int(math
.log(intlv_size
, 2))
103 # Use basic hashing for the channel selection, and preferably use
104 # the lower tag bits from the last level cache. As we do not know
105 # the details of the caches here, make an educated guess. 4 MByte
106 # 4-way associative with 64 byte cache lines is 6 offset bits and
110 # Create an instance so we can figure out the address
111 # mapping and row-buffer size
114 # Only do this for DRAMs
115 if issubclass(cls
, m5
.objects
.DRAMCtrl
):
116 # Inform each controller how many channels to account
118 ctrl
.channels
= nbr_mem_ctrls
120 # If the channel bits are appearing after the column
121 # bits, we need to add the appropriate number of bits
122 # for the row buffer size
123 if ctrl
.addr_mapping
.value
== 'RoRaBaChCo':
124 # This computation only really needs to happen
125 # once, but as we rely on having an instance we
126 # end up having to repeat it for each and every
128 rowbuffer_size
= ctrl
.device_rowbuffer_size
.value
* \
129 ctrl
.devices_per_rank
.value
131 intlv_low_bit
= int(math
.log(rowbuffer_size
, 2))
133 # We got all we need to configure the appropriate address
135 ctrl
.range = m5
.objects
.AddrRange(r
.start
, size
= r
.size(),
137 intlv_low_bit
+ intlv_bits
- 1,
139 xor_low_bit
+ intlv_bits
- 1,
140 intlvBits
= intlv_bits
,
144 def config_mem(options
, system
):
146 Create the memory controllers based on the options and attach them.
148 If requested, we make a multi-channel configuration of the
149 selected memory controller class by creating multiple instances of
150 the specific class. The individual controllers have their
151 parameters set such that the address range is interleaved between
155 if ( options
.mem_type
== "HMC_2500_x32"):
156 HMChost
= HMC
.config_host_hmc(options
, system
)
157 HMC
.config_hmc(options
, system
, HMChost
.hmc_host
)
158 subsystem
= system
.hmc_dev
159 xbar
= system
.hmc_dev
.xbar
164 if options
.tlm_memory
:
165 system
.external_memory
= m5
.objects
.ExternalSlave(
166 port_type
="tlm_slave",
167 port_data
=options
.tlm_memory
,
168 port
=system
.membus
.master
,
169 addr_ranges
=system
.mem_ranges
)
170 system
.kernel_addr_check
= False
173 if options
.external_memory_system
:
174 subsystem
.external_memory
= m5
.objects
.ExternalSlave(
175 port_type
=options
.external_memory_system
,
176 port_data
="init_mem0", port
=xbar
.master
,
177 addr_ranges
=system
.mem_ranges
)
178 subsystem
.kernel_addr_check
= False
181 nbr_mem_ctrls
= options
.mem_channels
183 from m5
.util
import fatal
184 intlv_bits
= int(math
.log(nbr_mem_ctrls
, 2))
185 if 2 ** intlv_bits
!= nbr_mem_ctrls
:
186 fatal("Number of memory channels must be a power of 2")
188 cls
= get(options
.mem_type
)
191 if options
.elastic_trace_en
and not issubclass(cls
, \
192 m5
.objects
.SimpleMemory
):
193 fatal("When elastic trace is enabled, configure mem-type as "
196 # The default behaviour is to interleave memory channels on 128
197 # byte granularity, or cache line granularity if larger than 128
198 # byte. This value is based on the locality seen across a large
199 # range of workloads.
200 intlv_size
= max(128, system
.cache_line_size
.value
)
202 # For every range (most systems will only have one), create an
203 # array of controllers and set their parameters to match their
204 # address mapping in the case of a DRAM
205 for r
in system
.mem_ranges
:
206 for i
in xrange(nbr_mem_ctrls
):
207 mem_ctrl
= create_mem_ctrl(cls
, r
, i
, nbr_mem_ctrls
, intlv_bits
,
209 # Set the number of ranks based on the command-line
210 # options if it was explicitly set
211 if issubclass(cls
, m5
.objects
.DRAMCtrl
) and \
213 mem_ctrl
.ranks_per_channel
= options
.mem_ranks
215 if options
.elastic_trace_en
:
216 mem_ctrl
.latency
= '1ns'
217 print "For elastic trace, over-riding Simple Memory " \
220 mem_ctrls
.append(mem_ctrl
)
222 subsystem
.mem_ctrls
= mem_ctrls
224 # Connect the controllers to the membus
225 for i
in xrange(len(subsystem
.mem_ctrls
)):
226 if (options
.mem_type
== "HMC_2500_x32"):
227 subsystem
.mem_ctrls
[i
].port
= xbar
[i
/4].master
229 subsystem
.mem_ctrls
[i
].port
= xbar
.master