configs/common/MemConfig.py

   1 # Copyright (c) 2013 ARM Limited
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  35 #
  36 # Authors: Andreas Sandberg
  37 #          Andreas Hansson
  38
  39 import m5.objects
  40 import inspect
  41 import sys
  42 from textwrap import  TextWrapper
  43
  44 # Dictionary of mapping names of real memory controller models to
  45 # classes.
  46 _mem_classes = {}
  47
  48 # Memory aliases. We make sure they exist before we add them to the
  49 # fina; list. A target may be specified as a tuple, in which case the
  50 # first available memory controller model in the tuple will be used.
  51 _mem_aliases_all = [
  52     ("simple_mem", "SimpleMemory"),
  53     ("ddr3_1600_x64", "DDR3_1600_x64"),
  54     ("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
  55     ("lpddr3_1600_x32", "LPDDR3_1600_x32"),
  56     ("wio_200_x128", "WideIO_200_x128"),
  57     ("dramsim2", "DRAMSim2")
  58     ]
  59
  60 # Filtered list of aliases. Only aliases for existing memory
  61 # controllers exist in this list.
  62 _mem_aliases = {}
  63
  64
  65 def is_mem_class(cls):
  66     """Determine if a class is a memory controller that can be instantiated"""
  67
  68     # We can't use the normal inspect.isclass because the ParamFactory
  69     # and ProxyFactory classes have a tendency to confuse it.
  70     try:
  71         return issubclass(cls, m5.objects.AbstractMemory) and \
  72             not cls.abstract
  73     except TypeError:
  74         return False
  75
  76 def get(name):
  77     """Get a memory class from a user provided class name or alias."""
  78
  79     real_name = _mem_aliases.get(name, name)
  80
  81     try:
  82         mem_class = _mem_classes[real_name]
  83         return mem_class
  84     except KeyError:
  85         print "%s is not a valid memory controller." % (name,)
  86         sys.exit(1)
  87
  88 def print_mem_list():
  89     """Print a list of available memory classes including their aliases."""
  90
  91     print "Available memory classes:"
  92     doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
  93     for name, cls in _mem_classes.items():
  94         print "\t%s" % name
  95
  96         # Try to extract the class documentation from the class help
  97         # string.
  98         doc = inspect.getdoc(cls)
  99         if doc:
 100             for line in doc_wrapper.wrap(doc):
 101                 print line
 102
 103     if _mem_aliases:
 104         print "\nMemory aliases:"
 105         for alias, target in _mem_aliases.items():
 106             print "\t%s => %s" % (alias, target)
 107
 108 def mem_names():
 109     """Return a list of valid memory names."""
 110     return _mem_classes.keys() + _mem_aliases.keys()
 111
 112 # Add all memory controllers in the object hierarchy.
 113 for name, cls in inspect.getmembers(m5.objects, is_mem_class):
 114     _mem_classes[name] = cls
 115
 116 for alias, target in _mem_aliases_all:
 117     if isinstance(target, tuple):
 118         # Some aliases contain a list of memory controller models
 119         # sorted in priority order. Use the first target that's
 120         # available.
 121         for t in target:
 122             if t in _mem_classes:
 123                 _mem_aliases[alias] = t
 124                 break
 125     elif target in _mem_classes:
 126         # Normal alias
 127         _mem_aliases[alias] = target
 128
 129 def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, cache_line_size):
 130     """
 131     Helper function for creating a single memoy controller from the given
 132     options.  This function is invoked multiple times in config_mem function
 133     to create an array of controllers.
 134     """
 135
 136     import math
 137     # The default behaviour is to interleave on cache line granularity
 138     cache_line_bit = int(math.log(cache_line_size, 2)) - 1
 139     intlv_low_bit = cache_line_bit
 140
 141     # Create an instance so we can figure out the address
 142     # mapping and row-buffer size
 143     ctrl = cls()
 144
 145     # Only do this for DRAMs
 146     if issubclass(cls, m5.objects.DRAMCtrl):
 147         # Inform each controller how many channels to account
 148         # for
 149         ctrl.channels = nbr_mem_ctrls
 150
 151         # If the channel bits are appearing after the column
 152         # bits, we need to add the appropriate number of bits
 153         # for the row buffer size
 154         if ctrl.addr_mapping.value == 'RoRaBaChCo':
 155             # This computation only really needs to happen
 156             # once, but as we rely on having an instance we
 157             # end up having to repeat it for each and every
 158             # one
 159             rowbuffer_size = ctrl.device_rowbuffer_size.value * \
 160                 ctrl.devices_per_rank.value
 161
 162             intlv_low_bit = int(math.log(rowbuffer_size, 2)) - 1
 163
 164     # We got all we need to configure the appropriate address
 165     # range
 166     ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
 167                                       intlvHighBit = \
 168                                           intlv_low_bit + intlv_bits,
 169                                       intlvBits = intlv_bits,
 170                                       intlvMatch = i)
 171     return ctrl
 172
 173 def config_mem(options, system):
 174     """
 175     Create the memory controllers based on the options and attach them.
 176
 177     If requested, we make a multi-channel configuration of the
 178     selected memory controller class by creating multiple instances of
 179     the specific class. The individual controllers have their
 180     parameters set such that the address range is interleaved between
 181     them.
 182     """
 183
 184     nbr_mem_ctrls = options.mem_channels
 185     import math
 186     from m5.util import fatal
 187     intlv_bits = int(math.log(nbr_mem_ctrls, 2))
 188     if 2 ** intlv_bits != nbr_mem_ctrls:
 189         fatal("Number of memory channels must be a power of 2")
 190
 191     cls = get(options.mem_type)
 192     mem_ctrls = []
 193
 194     # For every range (most systems will only have one), create an
 195     # array of controllers and set their parameters to match their
 196     # address mapping in the case of a DRAM
 197     for r in system.mem_ranges:
 198         for i in xrange(nbr_mem_ctrls):
 199             mem_ctrls.append(create_mem_ctrl(cls, r, i, nbr_mem_ctrls,
 200                                              intlv_bits,
 201                                              system.cache_line_size.value))
 202
 203     system.mem_ctrls = mem_ctrls
 204
 205     # Connect the controllers to the membus
 206     for i in xrange(len(system.mem_ctrls)):
 207         system.mem_ctrls[i].port = system.membus.master