configs/common/O3_ARM_v7a.py

   1 # Copyright (c) 2012 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Ron Dreslinski
  28
  29
  30 from m5.objects import *
  31
  32 # Simple ALU Instructions have a latency of 1
  33 class O3_ARM_v7a_Simple_Int(FUDesc):
  34     opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
  35     count = 2
  36
  37 # Complex ALU instructions have a variable latencies
  38 class O3_ARM_v7a_Complex_Int(FUDesc):
  39     opList = [ OpDesc(opClass='IntMult', opLat=3, issueLat=1),
  40                OpDesc(opClass='IntDiv', opLat=12, issueLat=12),
  41                OpDesc(opClass='IprAccess', opLat=3, issueLat=1) ]
  42     count = 1
  43
  44
  45 # Floating point and SIMD instructions
  46 class O3_ARM_v7a_FP(FUDesc):
  47     opList = [ OpDesc(opClass='SimdAdd', opLat=4),
  48                OpDesc(opClass='SimdAddAcc', opLat=4),
  49                OpDesc(opClass='SimdAlu', opLat=4),
  50                OpDesc(opClass='SimdCmp', opLat=4),
  51                OpDesc(opClass='SimdCvt', opLat=3),
  52                OpDesc(opClass='SimdMisc', opLat=3),
  53                OpDesc(opClass='SimdMult',opLat=5),
  54                OpDesc(opClass='SimdMultAcc',opLat=5),
  55                OpDesc(opClass='SimdShift',opLat=3),
  56                OpDesc(opClass='SimdShiftAcc', opLat=3),
  57                OpDesc(opClass='SimdSqrt', opLat=9),
  58                OpDesc(opClass='SimdFloatAdd',opLat=5),
  59                OpDesc(opClass='SimdFloatAlu',opLat=5),
  60                OpDesc(opClass='SimdFloatCmp', opLat=3),
  61                OpDesc(opClass='SimdFloatCvt', opLat=3),
  62                OpDesc(opClass='SimdFloatDiv', opLat=3),
  63                OpDesc(opClass='SimdFloatMisc', opLat=3),
  64                OpDesc(opClass='SimdFloatMult', opLat=3),
  65                OpDesc(opClass='SimdFloatMultAcc',opLat=1),
  66                OpDesc(opClass='SimdFloatSqrt', opLat=9),
  67                OpDesc(opClass='FloatAdd', opLat=5),
  68                OpDesc(opClass='FloatCmp', opLat=5),
  69                OpDesc(opClass='FloatCvt', opLat=5),
  70                OpDesc(opClass='FloatDiv', opLat=9, issueLat=9),
  71                OpDesc(opClass='FloatSqrt', opLat=33, issueLat=33),
  72                OpDesc(opClass='FloatMult', opLat=4) ]
  73     count = 2
  74
  75
  76 # Load/Store Units
  77 class O3_ARM_v7a_Load(FUDesc):
  78     opList = [ OpDesc(opClass='MemRead',opLat=2) ]
  79     count = 1
  80
  81 class O3_ARM_v7a_Store(FUDesc):
  82     opList = [OpDesc(opClass='MemWrite',opLat=2) ]
  83     count = 1
  84
  85 # Functional Units for this CPU
  86 class O3_ARM_v7a_FUP(FUPool):
  87     FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
  88               O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
  89
  90
  91 class O3_ARM_v7a_3(DerivO3CPU):
  92     predType = "tournament"
  93     localPredictorSize = 64
  94     localCtrBits = 2
  95     localHistoryTableSize = 64
  96     localHistoryBits = 6
  97     globalPredictorSize = 8192
  98     globalCtrBits = 2
  99     globalHistoryBits = 13
 100     choicePredictorSize = 8192
 101     choiceCtrBits = 2
 102     BTBEntries = 2048
 103     BTBTagSize = 18
 104     RASSize = 16
 105     instShiftAmt = 2
 106     LQEntries = 16
 107     SQEntries = 16
 108     LSQDepCheckShift = 0
 109     LFSTSize = 1024
 110     SSITSize = 1024
 111     decodeToFetchDelay = 1
 112     renameToFetchDelay = 1
 113     iewToFetchDelay = 1
 114     commitToFetchDelay = 1
 115     renameToDecodeDelay = 1
 116     iewToDecodeDelay = 1
 117     commitToDecodeDelay = 1
 118     iewToRenameDelay = 1
 119     commitToRenameDelay = 1
 120     commitToIEWDelay = 1
 121     fetchWidth = 3
 122     fetchToDecodeDelay = 3
 123     decodeWidth = 3
 124     decodeToRenameDelay = 2
 125     renameWidth = 3
 126     renameToIEWDelay = 1
 127     issueToExecuteDelay = 1
 128     dispatchWidth = 6
 129     issueWidth = 8
 130     wbWidth = 8
 131     wbDepth = 1
 132     fuPool = O3_ARM_v7a_FUP()
 133     iewToCommitDelay = 1
 134     renameToROBDelay = 1
 135     commitWidth = 8
 136     squashWidth = 8
 137     trapLatency = 13
 138     backComSize = 5
 139     forwardComSize = 5
 140     numPhysIntRegs = 128
 141     numPhysFloatRegs = 128
 142     numIQEntries = 32
 143     numROBEntries = 40
 144
 145     defer_registration= False
 146
 147 # Instruction Cache
 148 class O3_ARM_v7a_ICache(BaseCache):
 149     hit_latency = 1
 150     response_latency = 1
 151     block_size = 64
 152     mshrs = 2
 153     tgts_per_mshr = 8
 154     size = '32kB'
 155     assoc = 2
 156     is_top_level = 'true'
 157
 158 # Data Cache
 159 class O3_ARM_v7a_DCache(BaseCache):
 160     hit_latency = 2
 161     response_latency = 2
 162     block_size = 64
 163     mshrs = 6
 164     tgts_per_mshr = 8
 165     size = '32kB'
 166     assoc = 2
 167     write_buffers = 16
 168     is_top_level = 'true'
 169
 170 # TLB Cache
 171 # Use a cache as a L2 TLB
 172 class O3_ARM_v7aWalkCache(BaseCache):
 173     hit_latency = 4
 174     response_latency = 4
 175     block_size = 64
 176     mshrs = 6
 177     tgts_per_mshr = 8
 178     size = '1kB'
 179     assoc = 8
 180     write_buffers = 16
 181     is_top_level = 'true'
 182
 183
 184 # L2 Cache
 185 class O3_ARM_v7aL2(BaseCache):
 186     hit_latency = 12
 187     response_latency = 12
 188     block_size = 64
 189     mshrs = 16
 190     tgts_per_mshr = 8
 191     size = '1MB'
 192     assoc = 16
 193     write_buffers = 8
 194     prefetch_on_access = 'true'
 195     # Simple stride prefetcher
 196     prefetcher = StridePrefetcher(degree=8, latency = 1)
 197