1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 from os
.path
import join
as joinpath
32 from m5
.objects
import *
33 m5
.AddToPath('../common')
34 from Caches
import L1Cache
36 def setCPUClass(options
):
40 TmpClass
= TimingSimpleCPU
41 elif options
.detailed
:
42 if not options
.caches
:
43 print "O3 CPU must be used with caches"
47 TmpClass
= AtomicSimpleCPU
51 test_mem_mode
= 'atomic'
54 if options
.checkpoint_restore
:
56 TmpClass
= AtomicSimpleCPU
58 test_mem_mode
= 'timing'
60 return (TmpClass
, test_mem_mode
, CPUClass
)
63 def run(options
, root
, testsys
, cpu_class
):
65 maxtick
= options
.maxtick
67 simtime
= m5
.ticks
.seconds(simtime
)
68 print "simulating for: ", simtime
73 if options
.checkpoint_dir
:
74 cptdir
= options
.checkpoint_dir
75 elif m5
.options
.outdir
:
76 cptdir
= m5
.options
.outdir
81 max_checkpoints
= options
.max_checkpoints
85 switch_cpus
= [cpu_class(defer_registration
=True, cpu_id
=(np
+i
))
89 switch_cpus
[i
].system
= testsys
90 if not m5
.build_env
['FULL_SYSTEM']:
91 switch_cpus
[i
].workload
= testsys
.cpu
[i
].workload
92 switch_cpus
[i
].clock
= testsys
.cpu
[0].clock
94 root
.switch_cpus
= switch_cpus
95 switch_cpu_list
= [(testsys
.cpu
[i
], switch_cpus
[i
]) for i
in xrange(np
)]
97 if options
.standard_switch
:
98 switch_cpus
= [TimingSimpleCPU(defer_registration
=True, cpu_id
=(np
+i
))
100 switch_cpus_1
= [DerivO3CPU(defer_registration
=True, cpu_id
=(2*np
+i
))
104 switch_cpus
[i
].system
= testsys
105 switch_cpus_1
[i
].system
= testsys
106 if not m5
.build_env
['FULL_SYSTEM']:
107 switch_cpus
[i
].workload
= testsys
.cpu
[i
].workload
108 switch_cpus_1
[i
].workload
= testsys
.cpu
[i
].workload
109 switch_cpus
[i
].clock
= testsys
.cpu
[0].clock
110 switch_cpus_1
[i
].clock
= testsys
.cpu
[0].clock
112 if not options
.caches
:
113 # O3 CPU must have a cache to work.
114 switch_cpus_1
[i
].addPrivateSplitL1Caches(L1Cache(size
= '32kB'),
115 L1Cache(size
= '64kB'))
116 switch_cpus_1
[i
].connectMemPorts(testsys
.membus
)
119 testsys
.switch_cpus
= switch_cpus
120 testsys
.switch_cpus_1
= switch_cpus_1
121 switch_cpu_list
= [(testsys
.cpu
[i
], switch_cpus
[i
]) for i
in xrange(np
)]
122 switch_cpu_list1
= [(switch_cpus
[i
], switch_cpus_1
[i
]) for i
in xrange(np
)]
126 if options
.checkpoint_restore
:
127 from os
.path
import isdir
128 from os
import listdir
131 if not isdir(cptdir
):
132 m5
.panic("checkpoint dir %s does not exist!" % cptdir
)
134 dirs
= listdir(cptdir
)
135 expr
= re
.compile('cpt\.([0-9]*)')
138 match
= expr
.match(dir)
140 cpts
.append(match
.group(1))
142 cpts
.sort(lambda a
,b
: cmp(long(a
), long(b
)))
144 cpt_num
= options
.checkpoint_restore
146 if cpt_num
> len(cpts
):
147 m5
.panic('Checkpoint %d not found' % cpt_num
)
149 ## Adjust max tick based on our starting tick
150 maxtick
= maxtick
- int(cpts
[cpt_num
- 1])
152 ## Restore the checkpoint
153 m5
.restoreCheckpoint(root
,
154 joinpath(cptdir
, "cpt.%s" % cpts
[cpt_num
- 1]))
156 if options
.standard_switch
or cpu_class
:
157 exit_event
= m5
.simulate(10000)
159 ## when you change to Timing (or Atomic), you halt the system given
160 ## as argument. When you are finished with the system changes
161 ## (including switchCpus), you must resume the system manually.
162 ## You DON'T need to resume after just switching CPUs if you haven't
163 ## changed anything on the system level.
165 m5
.changeToTiming(testsys
)
166 m5
.switchCpus(switch_cpu_list
)
169 if options
.standard_switch
:
170 exit_event
= m5
.simulate(options
.warmup
)
172 m5
.switchCpus(switch_cpu_list1
)
178 ## Checkpoints being taken via the command line at <when> and at subsequent
179 ## periods of <period>. Checkpoint instructions received from the benchmark running
180 ## are ignored and skipped in favor of command line checkpoint instructions.
181 if options
.take_checkpoints
:
182 [when
, period
] = options
.take_checkpoints
.split(",", 1)
186 exit_event
= m5
.simulate(when
)
187 while exit_event
.getCause() == "checkpoint":
188 exit_event
= m5
.simulate(when
- m5
.curTick())
190 if exit_event
.getCause() == "simulate() limit reached":
191 m5
.checkpoint(root
, joinpath(cptdir
, "cpt.%d"))
195 exit_cause
= "maximum %d checkpoints dropped" % max_checkpoints
196 while num_checkpoints
< max_checkpoints
and \
197 exit_event
.getCause() == "simulate() limit reached":
198 if (sim_ticks
+ period
) > maxtick
:
199 exit_event
= m5
.simulate(maxtick
- sim_ticks
)
200 exit_cause
= exit_event
.getCause()
203 exit_event
= m5
.simulate(period
)
205 while exit_event
.getCause() == "checkpoint":
206 exit_event
= m5
.simulate(sim_ticks
- m5
.curTick())
207 if exit_event
.getCause() == "simulate() limit reached":
208 m5
.checkpoint(root
, joinpath(cptdir
, "cpt.%d"))
211 if exit_event
.getCause() != "simulate() limit reached":
212 exit_cause
= exit_event
.getCause();
215 else: #no checkpoints being taken via this script
216 exit_event
= m5
.simulate(maxtick
)
218 while exit_event
.getCause() == "checkpoint":
219 m5
.checkpoint(root
, joinpath(cptdir
, "cpt.%d"))
221 if num_checkpoints
== max_checkpoints
:
222 exit_cause
= "maximum %d checkpoints dropped" % max_checkpoints
225 exit_event
= m5
.simulate(maxtick
- m5
.curTick())
226 exit_cause
= exit_event
.getCause()
229 exit_cause
= exit_event
.getCause()
230 print 'Exiting @ cycle %i because %s' % (m5
.curTick(), exit_cause
)