configs/common/Simulation.py

   1 # Copyright (c) 2006 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Lisa Hsu
  28
  29 from os import getcwd
  30 import m5
  31 from m5.objects import *
  32 m5.AddToPath('../common')
  33 from Caches import L1Cache
  34
  35 def setCPUClass(options):
  36
  37     atomic = False
  38     if options.timing:
  39         TmpClass = TimingSimpleCPU
  40     elif options.detailed:
  41         TmpClass = DerivO3CPU
  42     else:
  43         TmpClass = AtomicSimpleCPU
  44         atomic = True
  45
  46     CPUClass = None
  47     test_mem_mode = 'atomic'
  48
  49     if not atomic:
  50         if options.checkpoint_restore:
  51             CPUClass = TmpClass
  52             TmpClass = AtomicSimpleCPU
  53         else:
  54             test_mem_mode = 'timing'
  55
  56     return (TmpClass, test_mem_mode, CPUClass)
  57
  58
  59 def run(options, root, testsys, cpu_class):
  60     if options.maxtick:
  61         maxtick = options.maxtick
  62     elif options.maxtime:
  63         simtime = int(options.maxtime * root.clock.value)
  64         print "simulating for: ", simtime
  65         maxtick = simtime
  66     else:
  67         maxtick = -1
  68
  69     if options.checkpoint_dir:
  70         cptdir = options.checkpoint_dir
  71     else:
  72         cptdir = getcwd()
  73
  74     np = options.num_cpus
  75     max_checkpoints = options.max_checkpoints
  76     switch_cpus = None
  77
  78     if cpu_class:
  79         switch_cpus = [cpu_class(defer_registration=True, cpu_id=(np+i))
  80                        for i in xrange(np)]
  81
  82         for i in xrange(np):
  83             switch_cpus[i].system =  testsys
  84             if not m5.build_env['FULL_SYSTEM']:
  85                 switch_cpus[i].workload = testsys.cpu[i].workload
  86             switch_cpus[i].clock = testsys.cpu[0].clock
  87             if options.caches:
  88                 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
  89                                                        L1Cache(size = '64kB'))
  90                 switch_cpus[i].connectMemPorts(testsys.membus)
  91
  92         root.switch_cpus = switch_cpus
  93         switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
  94
  95     if options.standard_switch:
  96         switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
  97                        for i in xrange(np)]
  98         switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
  99                         for i in xrange(np)]
 100
 101         for i in xrange(np):
 102             switch_cpus[i].system =  testsys
 103             switch_cpus_1[i].system =  testsys
 104             if not m5.build_env['FULL_SYSTEM']:
 105                 switch_cpus[i].workload = testsys.cpu[i].workload
 106                 switch_cpus_1[i].workload = testsys.cpu[i].workload
 107             switch_cpus[i].clock = testsys.cpu[0].clock
 108             switch_cpus_1[i].clock = testsys.cpu[0].clock
 109
 110             if options.caches:
 111                 switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
 112                                                        L1Cache(size = '64kB'))
 113                 switch_cpus[i].connectMemPorts(testsys.membus)
 114             else:
 115                 # O3 CPU must have a cache to work.
 116                 switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
 117                                                          L1Cache(size = '64kB'))
 118                 switch_cpus_1[i].connectMemPorts(testsys.membus)
 119
 120
 121             root.switch_cpus = switch_cpus
 122             root.switch_cpus_1 = switch_cpus_1
 123             switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
 124             switch_cpu_list1 = [(switch_cpus[i], switch_cpus_1[i]) for i in xrange(np)]
 125
 126     m5.instantiate(root)
 127
 128     if options.checkpoint_restore:
 129         from os.path import isdir
 130         from os import listdir
 131         import re
 132
 133         if not isdir(cptdir):
 134             m5.panic("checkpoint dir %s does not exist!" % cptdir)
 135
 136         dirs = listdir(cptdir)
 137         expr = re.compile('cpt.([0-9]*)')
 138         cpts = []
 139         for dir in dirs:
 140             match = expr.match(dir)
 141             if match:
 142                 cpts.append(match.group(1))
 143
 144         cpts.sort(lambda a,b: cmp(long(a), long(b)))
 145
 146         cpt_num = options.checkpoint_restore
 147
 148         if cpt_num > len(cpts):
 149             m5.panic('Checkpoint %d not found' % cpt_num)
 150
 151         m5.restoreCheckpoint(root,
 152                              "/".join([cptdir, "cpt.%s" % cpts[cpt_num - 1]]))
 153
 154     if options.standard_switch or cpu_class:
 155         exit_event = m5.simulate(10000)
 156
 157         ## when you change to Timing (or Atomic), you halt the system given
 158         ## as argument.  When you are finished with the system changes
 159         ## (including switchCpus), you must resume the system manually.
 160         ## You DON'T need to resume after just switching CPUs if you haven't
 161         ## changed anything on the system level.
 162
 163         m5.changeToTiming(testsys)
 164         m5.switchCpus(switch_cpu_list)
 165         m5.resume(testsys)
 166
 167         if options.standard_switch:
 168             exit_event = m5.simulate(options.warmup)
 169             m5.switchCpus(switch_cpu_list1)
 170
 171     num_checkpoints = 0
 172     exit_cause = ''
 173
 174     ## Checkpoints being taken via the command line at <when> and at subsequent
 175     ## periods of <period>.  Checkpoint instructions received from the benchmark running
 176     ## are ignored and skipped in favor of command line checkpoint instructions.
 177     if options.take_checkpoints:
 178         [when, period] = options.take_checkpoints.split(",", 1)
 179         when = int(when)
 180         period = int(period)
 181
 182         exit_event = m5.simulate(when)
 183         while exit_event.getCause() == "checkpoint":
 184             exit_event = m5.simulate(when - m5.curTick())
 185
 186         if exit_event.getCause() == "simulate() limit reached":
 187             m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
 188             num_checkpoints += 1
 189
 190         sim_ticks = when
 191         exit_cause = "maximum %d checkpoints dropped" % max_checkpoints
 192         while num_checkpoints < max_checkpoints:
 193             if (sim_ticks + period) > maxtick and maxtick != -1:
 194                 exit_event = m5.simulate(maxtick - sim_ticks)
 195                 exit_cause = exit_event.getCause()
 196                 break
 197             else:
 198                 exit_event = m5.simulate(period)
 199                 sim_ticks += period
 200                 while exit_event.getCause() == "checkpoint":
 201                     exit_event = m5.simulate(sim_ticks - m5.curTick())
 202                 if exit_event.getCause() == "simulate() limit reached":
 203                     m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
 204                     num_checkpoints += 1
 205
 206     else: #no checkpoints being taken via this script
 207         exit_event = m5.simulate(maxtick)
 208
 209         while exit_event.getCause() == "checkpoint":
 210             m5.checkpoint(root, "/".join([cptdir,"cpt.%d"]))
 211             num_checkpoints += 1
 212             if num_checkpoints == max_checkpoints:
 213                 exit_cause =  "maximum %d checkpoints dropped" % max_checkpoints
 214                 break
 215
 216             if maxtick == -1:
 217                 exit_event = m5.simulate(maxtick)
 218             else:
 219                 exit_event = m5.simulate(maxtick - m5.curTick())
 220
 221             exit_cause = exit_event.getCause()
 222
 223     if exit_cause == '':
 224         exit_cause = exit_event.getCause()
 225     print 'Exiting @ cycle', m5.curTick(), 'because ', exit_cause
 226