1 # Copyright (c) 2006-2007 The Regents of The University of Michigan
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
6 # met: redistributions of source code must retain the above copyright
7 # notice, this list of conditions and the following disclaimer;
8 # redistributions in binary form must reproduce the above copyright
9 # notice, this list of conditions and the following disclaimer in the
10 # documentation and/or other materials provided with the distribution;
11 # neither the name of the copyright holders nor the names of its
12 # contributors may be used to endorse or promote products derived from
13 # this software without specific prior written permission.
15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 from os
.path
import join
as joinpath
32 from m5
.objects
import *
33 m5
.AddToPath('../common')
34 from Caches
import L1Cache
36 def setCPUClass(options
):
40 TmpClass
= TimingSimpleCPU
41 elif options
.detailed
:
42 if not options
.caches
:
43 print "O3 CPU must be used with caches"
47 TmpClass
= AtomicSimpleCPU
51 test_mem_mode
= 'atomic'
54 if options
.checkpoint_restore
:
56 TmpClass
= AtomicSimpleCPU
58 test_mem_mode
= 'timing'
60 return (TmpClass
, test_mem_mode
, CPUClass
)
63 def run(options
, root
, testsys
, cpu_class
):
65 maxtick
= options
.maxtick
67 simtime
= m5
.ticks
.seconds(simtime
)
68 print "simulating for: ", simtime
73 if options
.checkpoint_dir
:
74 cptdir
= options
.checkpoint_dir
79 max_checkpoints
= options
.max_checkpoints
83 switch_cpus
= [cpu_class(defer_registration
=True, cpu_id
=(np
+i
))
87 switch_cpus
[i
].system
= testsys
88 if not m5
.build_env
['FULL_SYSTEM']:
89 switch_cpus
[i
].workload
= testsys
.cpu
[i
].workload
90 switch_cpus
[i
].clock
= testsys
.cpu
[0].clock
92 root
.switch_cpus
= switch_cpus
93 switch_cpu_list
= [(testsys
.cpu
[i
], switch_cpus
[i
]) for i
in xrange(np
)]
95 if options
.standard_switch
:
96 switch_cpus
= [TimingSimpleCPU(defer_registration
=True, cpu_id
=(np
+i
))
98 switch_cpus_1
= [DerivO3CPU(defer_registration
=True, cpu_id
=(2*np
+i
))
102 switch_cpus
[i
].system
= testsys
103 switch_cpus_1
[i
].system
= testsys
104 if not m5
.build_env
['FULL_SYSTEM']:
105 switch_cpus
[i
].workload
= testsys
.cpu
[i
].workload
106 switch_cpus_1
[i
].workload
= testsys
.cpu
[i
].workload
107 switch_cpus
[i
].clock
= testsys
.cpu
[0].clock
108 switch_cpus_1
[i
].clock
= testsys
.cpu
[0].clock
110 if not options
.caches
:
111 # O3 CPU must have a cache to work.
112 switch_cpus_1
[i
].addPrivateSplitL1Caches(L1Cache(size
= '32kB'),
113 L1Cache(size
= '64kB'))
114 switch_cpus_1
[i
].connectMemPorts(testsys
.membus
)
117 testsys
.switch_cpus
= switch_cpus
118 testsys
.switch_cpus_1
= switch_cpus_1
119 switch_cpu_list
= [(testsys
.cpu
[i
], switch_cpus
[i
]) for i
in xrange(np
)]
120 switch_cpu_list1
= [(switch_cpus
[i
], switch_cpus_1
[i
]) for i
in xrange(np
)]
124 if options
.checkpoint_restore
:
125 from os
.path
import isdir
126 from os
import listdir
129 if not isdir(cptdir
):
130 m5
.panic("checkpoint dir %s does not exist!" % cptdir
)
132 dirs
= listdir(cptdir
)
133 expr
= re
.compile('cpt.([0-9]*)')
136 match
= expr
.match(dir)
138 cpts
.append(match
.group(1))
140 cpts
.sort(lambda a
,b
: cmp(long(a
), long(b
)))
142 cpt_num
= options
.checkpoint_restore
144 if cpt_num
> len(cpts
):
145 m5
.panic('Checkpoint %d not found' % cpt_num
)
147 ## Adjust max tick based on our starting tick
148 maxtick
= maxtick
- int(cpts
[cpt_num
- 1])
150 ## Restore the checkpoint
151 m5
.restoreCheckpoint(root
,
152 joinpath(cptdir
, "cpt.%s" % cpts
[cpt_num
- 1]))
154 if options
.standard_switch
or cpu_class
:
155 exit_event
= m5
.simulate(10000)
157 ## when you change to Timing (or Atomic), you halt the system given
158 ## as argument. When you are finished with the system changes
159 ## (including switchCpus), you must resume the system manually.
160 ## You DON'T need to resume after just switching CPUs if you haven't
161 ## changed anything on the system level.
163 m5
.changeToTiming(testsys
)
164 m5
.switchCpus(switch_cpu_list
)
167 if options
.standard_switch
:
168 exit_event
= m5
.simulate(options
.warmup
)
169 m5
.switchCpus(switch_cpu_list1
)
174 ## Checkpoints being taken via the command line at <when> and at subsequent
175 ## periods of <period>. Checkpoint instructions received from the benchmark running
176 ## are ignored and skipped in favor of command line checkpoint instructions.
177 if options
.take_checkpoints
:
178 [when
, period
] = options
.take_checkpoints
.split(",", 1)
182 exit_event
= m5
.simulate(when
)
183 while exit_event
.getCause() == "checkpoint":
184 exit_event
= m5
.simulate(when
- m5
.curTick())
186 if exit_event
.getCause() == "simulate() limit reached":
187 m5
.checkpoint(root
, joinpath(cptdir
, "cpt.%d"))
191 exit_cause
= "maximum %d checkpoints dropped" % max_checkpoints
192 while num_checkpoints
< max_checkpoints
and \
193 exit_event
.getCause() != "user interrupt received":
194 if (sim_ticks
+ period
) > maxtick
:
195 exit_event
= m5
.simulate(maxtick
- sim_ticks
)
196 exit_cause
= exit_event
.getCause()
199 exit_event
= m5
.simulate(period
)
201 while exit_event
.getCause() == "checkpoint":
202 exit_event
= m5
.simulate(sim_ticks
- m5
.curTick())
203 if exit_event
.getCause() == "simulate() limit reached":
204 m5
.checkpoint(root
, joinpath(cptdir
, "cpt.%d"))
207 if exit_event
.getCause() == "user interrupt received":
208 exit_cause
= exit_event
.getCause();
211 else: #no checkpoints being taken via this script
212 exit_event
= m5
.simulate(maxtick
)
214 while exit_event
.getCause() == "checkpoint":
215 m5
.checkpoint(root
, joinpath(cptdir
, "cpt.%d"))
217 if num_checkpoints
== max_checkpoints
:
218 exit_cause
= "maximum %d checkpoints dropped" % max_checkpoints
221 exit_event
= m5
.simulate(maxtick
- m5
.curTick())
222 exit_cause
= exit_event
.getCause()
225 exit_cause
= exit_event
.getCause()
226 print 'Exiting @ cycle %i because %s' % (m5
.curTick(), exit_cause
)