configs/common/ex5_big.py

   1 # Copyright (c) 2012 The Regents of The University of Michigan
   2 # Copyright (c) 2016 Centre National de la Recherche Scientifique
   3 # All rights reserved.
   4 #
   5 # Redistribution and use in source and binary forms, with or without
   6 # modification, are permitted provided that the following conditions are
   7 # met: redistributions of source code must retain the above copyright
   8 # notice, this list of conditions and the following disclaimer;
   9 # redistributions in binary form must reproduce the above copyright
  10 # notice, this list of conditions and the following disclaimer in the
  11 # documentation and/or other materials provided with the distribution;
  12 # neither the name of the copyright holders nor the names of its
  13 # contributors may be used to endorse or promote products derived from
  14 # this software without specific prior written permission.
  15 #
  16 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27 #
  28 # Authors: Ron Dreslinski
  29 #          Anastasiia Butko
  30 #          Louisa Bessad
  31
  32 from m5.objects import *
  33 from O3_ARM_v7a import *
  34 from Caches import *
  35
  36 #-----------------------------------------------------------------------
  37 #                ex5 big core (based on the ARM Cortex-A15)
  38 #-----------------------------------------------------------------------
  39
  40 # Simple ALU Instructions have a latency of 1
  41 class ex5_big_Simple_Int(O3_ARM_v7a_Simple_Int):
  42     opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
  43     count = 2
  44
  45 # Complex ALU instructions have a variable latencies
  46 class ex5_big_Complex_Int(O3_ARM_v7a_Complex_Int):
  47     opList = [ OpDesc(opClass='IntMult', opLat=4, pipelined=True),
  48                OpDesc(opClass='IntDiv', opLat=11, pipelined=False),
  49                OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
  50     count = 1
  51
  52 # Floating point and SIMD instructions
  53 class ex5_big_FP(O3_ARM_v7a_FP):
  54     opList = [ OpDesc(opClass='SimdAdd', opLat=3),
  55                OpDesc(opClass='SimdAddAcc', opLat=4),
  56                OpDesc(opClass='SimdAlu', opLat=4),
  57                OpDesc(opClass='SimdCmp', opLat=4),
  58                OpDesc(opClass='SimdCvt', opLat=3),
  59                OpDesc(opClass='SimdMisc', opLat=3),
  60                OpDesc(opClass='SimdMult',opLat=6),
  61                OpDesc(opClass='SimdMultAcc',opLat=5),
  62                OpDesc(opClass='SimdShift',opLat=3),
  63                OpDesc(opClass='SimdShiftAcc', opLat=3),
  64                OpDesc(opClass='SimdSqrt', opLat=9),
  65                OpDesc(opClass='SimdFloatAdd',opLat=6),
  66                OpDesc(opClass='SimdFloatAlu',opLat=5),
  67                OpDesc(opClass='SimdFloatCmp', opLat=3),
  68                OpDesc(opClass='SimdFloatCvt', opLat=3),
  69                OpDesc(opClass='SimdFloatDiv', opLat=21),
  70                OpDesc(opClass='SimdFloatMisc', opLat=3),
  71                OpDesc(opClass='SimdFloatMult', opLat=6),
  72                OpDesc(opClass='SimdFloatMultAcc',opLat=1),
  73                OpDesc(opClass='SimdFloatSqrt', opLat=9),
  74                OpDesc(opClass='FloatAdd', opLat=6),
  75                OpDesc(opClass='FloatCmp', opLat=5),
  76                OpDesc(opClass='FloatCvt', opLat=5),
  77                OpDesc(opClass='FloatDiv', opLat=12, pipelined=False),
  78                OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
  79                OpDesc(opClass='FloatMult', opLat=8) ]
  80     count = 2
  81
  82
  83 # Load/Store Units
  84 class ex5_big_Load(O3_ARM_v7a_Load):
  85     opList = [ OpDesc(opClass='MemRead',opLat=2) ]
  86     count = 1
  87
  88 class ex5_big_Store(O3_ARM_v7a_Store):
  89     opList = [OpDesc(opClass='MemWrite',opLat=2) ]
  90     count = 1
  91
  92 # Functional Units for this CPU
  93 class ex5_big_FUP(O3_ARM_v7a_FUP):
  94     FUList = [ex5_big_Simple_Int(), ex5_big_Complex_Int(),
  95               ex5_big_Load(), ex5_big_Store(), ex5_big_FP()]
  96
  97 # Bi-Mode Branch Predictor
  98 class ex5_big_BP(O3_ARM_v7a_BP):
  99     globalPredictorSize = 4096
 100     globalCtrBits = 2
 101     choicePredictorSize = 1024
 102     choiceCtrBits = 3
 103     BTBEntries = 4096
 104     BTBTagSize = 18
 105     RASSize = 48
 106     instShiftAmt = 2
 107
 108 class ex5_big(O3_ARM_v7a_3):
 109     LQEntries = 16
 110     SQEntries = 16
 111     LSQDepCheckShift = 0
 112     LFSTSize = 1024
 113     SSITSize = 1024
 114     decodeToFetchDelay = 1
 115     renameToFetchDelay = 1
 116     iewToFetchDelay = 1
 117     commitToFetchDelay = 1
 118     renameToDecodeDelay = 1
 119     iewToDecodeDelay = 1
 120     commitToDecodeDelay = 1
 121     iewToRenameDelay = 1
 122     commitToRenameDelay = 1
 123     commitToIEWDelay = 1
 124     fetchWidth = 3
 125     fetchBufferSize = 16
 126     fetchToDecodeDelay = 3
 127     decodeWidth = 3
 128     decodeToRenameDelay = 2
 129     renameWidth = 3
 130     renameToIEWDelay = 1
 131     issueToExecuteDelay = 1
 132     dispatchWidth = 6
 133     issueWidth = 8
 134     wbWidth = 8
 135     fuPool = ex5_big_FUP()
 136     iewToCommitDelay = 1
 137     renameToROBDelay = 1
 138     commitWidth = 8
 139     squashWidth = 8
 140     trapLatency = 13
 141     backComSize = 5
 142     forwardComSize = 5
 143     numPhysIntRegs = 90
 144     numPhysFloatRegs = 256
 145     numIQEntries = 48
 146     numROBEntries = 60
 147
 148     switched_out = False
 149     branchPred = ex5_big_BP()
 150
 151 # Instruction Cache
 152 class L1I(O3_ARM_v7a_ICache):
 153     tag_latency = 2
 154     data_latency = 2
 155     response_latency = 2
 156     mshrs = 2
 157     tgts_per_mshr = 8
 158     size = '32kB'
 159     assoc = 2
 160     is_read_only = True
 161     # Writeback clean lines as well
 162     writeback_clean = True
 163
 164 # Data Cache
 165 class L1D(O3_ARM_v7a_DCache):
 166     tag_latency = 2
 167     data_latency = 2
 168     response_latency = 2
 169     mshrs = 6
 170     tgts_per_mshr = 8
 171     size = '32kB'
 172     assoc = 2
 173     write_buffers = 16
 174     # Consider the L2 a victim cache also for clean lines
 175     writeback_clean = True
 176
 177 # TLB Cache
 178 # Use a cache as a L2 TLB
 179 class WalkCache(O3_ARM_v7aWalkCache):
 180     tag_latency = 4
 181     data_latency = 4
 182     response_latency = 4
 183     mshrs = 6
 184     tgts_per_mshr = 8
 185     size = '1kB'
 186     assoc = 8
 187     write_buffers = 16
 188     is_read_only = True
 189     # Writeback clean lines as well
 190     writeback_clean = True
 191
 192 # L2 Cache
 193 class L2(O3_ARM_v7aL2):
 194     tag_latency = 15
 195     data_latency = 15
 196     response_latency = 15
 197     mshrs = 16
 198     tgts_per_mshr = 8
 199     size = '2MB'
 200     assoc = 16
 201     write_buffers = 8
 202     prefetch_on_access = True
 203     clusivity = 'mostly_excl'
 204     # Simple stride prefetcher
 205     prefetcher = StridePrefetcher(degree=8, latency = 1)
 206     tags = RandomRepl()