87917418d43ae71646693b1c3adab9734422f52b
1 # Copyright (c) 2015 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
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14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
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20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Hansson
43 from m5
.objects
import *
44 from m5
.util
import addToPath
45 from m5
.internal
.stats
import periodicStatDump
47 addToPath('../common')
50 addToPath('../../util')
53 # this script is helpful to observe the memory latency for various
54 # levels in a cache hierarchy, and various cache and memory
55 # configurations, in essence replicating the lmbench lat_mem_rd thrash
58 # import the packet proto definitions, and if they are not found,
59 # attempt to generate them automatically
63 print "Did not find packet proto definitions, attempting to generate"
64 from subprocess
import call
65 error
= call(['protoc', '--python_out=configs/dram',
66 '--proto_path=src/proto', 'src/proto/packet.proto'])
68 print "Generated packet proto definitions"
71 import google
.protobuf
73 print "Please install the Python protobuf module"
78 print "Failed to import packet proto definitions"
81 parser
= optparse
.OptionParser()
83 parser
.add_option("--mem-type", type="choice", default
="DDR3_1600_x64",
84 choices
=MemConfig
.mem_names(),
85 help = "type of memory to use")
86 parser
.add_option("--mem-size", action
="store", type="string",
88 help="Specify the memory size")
89 parser
.add_option("--reuse-trace", action
="store_true",
90 help="Prevent generation of traces and reuse existing")
92 (options
, args
) = parser
.parse_args()
95 print "Error: script doesn't take any positional arguments"
98 # start by creating the system itself, using a multi-layer 2.0 GHz
99 # crossbar, delivering 64 bytes / 3 cycles (one header cycle) which
100 # amounts to 42.7 GByte/s per layer and thus per port
101 system
= System(membus
= SystemXBar(width
= 32))
102 system
.clk_domain
= SrcClockDomain(clock
= '2.0GHz',
104 VoltageDomain(voltage
= '1V'))
106 mem_range
= AddrRange(options
.mem_size
)
107 system
.mem_ranges
= [mem_range
]
109 # do not worry about reserving space for the backing store
110 system
.mmap_using_noreserve
= True
112 # currently not exposed as command-line options, set here for now
113 options
.mem_channels
= 1
114 options
.mem_ranks
= 1
115 options
.external_memory_system
= 0
116 options
.tlm_memory
= 0
117 options
.elastic_trace_en
= 0
119 MemConfig
.config_mem(options
, system
)
121 # there is no point slowing things down by saving any data
122 for ctrl
in system
.mem_ctrls
:
125 # the following assumes that we are using the native DRAM
126 # controller, check to be sure
127 if isinstance(ctrl
, m5
.objects
.DRAMCtrl
):
128 # make the DRAM refresh interval sufficiently infinite to avoid
132 # use the same concept as the utilisation sweep, and print the config
133 # so that we can later read it in
134 cfg_file_name
= os
.path
.join(m5
.options
.outdir
, "lat_mem_rd.cfg")
135 cfg_file
= open(cfg_file_name
, 'w')
137 # set an appropriate burst length in bytes
139 system
.cache_line_size
= burst_size
141 # lazy version to check if an integer is a power of two
143 return num
!= 0 and ((num
& (num
- 1)) == 0)
145 # assume we start every range at 0
146 max_range
= int(mem_range
.end
)
148 # start at a size of 4 kByte, and go up till we hit the max, increase
149 # the step every time we hit a power of two
154 while ranges
[-1] < max_range
:
155 new_range
= ranges
[-1] + step
156 if is_pow2(new_range
):
158 ranges
.append(new_range
)
160 # how many times to repeat the measurement for each data point
163 # 150 ns in ticks, this is choosen to be high enough that transactions
164 # do not pile up in the system, adjust if needed
167 # for every data point, we create a trace containing a random address
168 # sequence, so that we can play back the same sequence for warming and
169 # the actual measurement
170 def create_trace(filename
, max_addr
, burst_size
, itt
):
172 proto_out
= gzip
.open(filename
, 'wb')
174 print "Failed to open ", filename
, " for writing"
177 # write the magic number in 4-byte Little Endian, similar to what
178 # is done in src/proto/protoio.cc
179 proto_out
.write("gem5")
181 # add the packet header
182 header
= packet_pb2
.PacketHeader()
183 header
.obj_id
= "lat_mem_rd for range 0:" + str(max_addr
)
184 # assume the default tick rate (1 ps)
185 header
.tick_freq
= 1000000000000
186 protolib
.encodeMessage(proto_out
, header
)
188 # create a list of every single address to touch
189 addrs
= range(0, max_addr
, burst_size
)
192 random
.shuffle(addrs
)
196 # create a packet we can re-use for all the addresses
197 packet
= packet_pb2
.Packet()
198 # ReadReq is 1 in src/mem/packet.hh Command enum
200 packet
.size
= int(burst_size
)
203 packet
.tick
= long(tick
)
204 packet
.addr
= long(addr
)
205 protolib
.encodeMessage(proto_out
, packet
)
210 # this will take a while, so keep the user informed
211 print "Generating traces, please wait..."
215 period
= long(itt
* (max_range
/ burst_size
))
217 # now we create the states for each range
219 filename
= os
.path
.join(m5
.options
.outdir
,
220 'lat_mem_rd%d.trc.gz' % nxt_range
)
222 if not options
.reuse_trace
:
223 # create the actual random trace for this range
224 create_trace(filename
, r
, burst_size
, itt
)
227 cfg_file
.write("STATE %d %d TRACE %s 0\n" %
228 (nxt_state
, period
, filename
))
229 nxt_state
= nxt_state
+ 1
231 # the measuring states
232 for i
in range(iterations
):
233 cfg_file
.write("STATE %d %d TRACE %s 0\n" %
234 (nxt_state
, period
, filename
))
235 nxt_state
= nxt_state
+ 1
237 nxt_range
= nxt_range
+ 1
239 cfg_file
.write("INIT 0\n")
241 # go through the states one by one
242 for state
in range(1, nxt_state
):
243 cfg_file
.write("TRANSITION %d %d 1\n" % (state
- 1, state
))
245 cfg_file
.write("TRANSITION %d %d 1\n" % (nxt_state
- 1, nxt_state
- 1))
249 # create a traffic generator, and point it to the file we just created
250 system
.tgen
= TrafficGen(config_file
= cfg_file_name
)
252 # add a communication monitor
253 system
.monitor
= CommMonitor()
255 # connect the traffic generator to the system
256 system
.tgen
.port
= system
.monitor
.slave
258 # create the actual cache hierarchy, for now just go with something
259 # basic to explore some of the options
262 # a starting point for an L3 cache
263 class L3Cache(Cache
):
266 response_latency
= 40
271 # note that everything is in the same clock domain, 2.0 GHz as
273 system
.l1cache
= L1_DCache(size
= '64kB')
274 system
.monitor
.master
= system
.l1cache
.cpu_side
276 system
.l2cache
= L2Cache(size
= '512kB', writeback_clean
= True)
277 system
.l2cache
.xbar
= L2XBar()
278 system
.l1cache
.mem_side
= system
.l2cache
.xbar
.slave
279 system
.l2cache
.cpu_side
= system
.l2cache
.xbar
.master
281 # make the L3 mostly exclusive, and correspondingly ensure that the L2
282 # writes back also clean lines to the L3
283 system
.l3cache
= L3Cache(size
= '4MB', clusivity
= 'mostly_excl')
284 system
.l3cache
.xbar
= L2XBar()
285 system
.l2cache
.mem_side
= system
.l3cache
.xbar
.slave
286 system
.l3cache
.cpu_side
= system
.l3cache
.xbar
.master
287 system
.l3cache
.mem_side
= system
.membus
.slave
289 # connect the system port even if it is not used in this example
290 system
.system_port
= system
.membus
.slave
292 # every period, dump and reset all stats
293 periodicStatDump(period
)
296 root
= Root(full_system
= False, system
= system
)
297 root
.system
.mem_mode
= 'timing'
300 m5
.simulate(nxt_state
* period
)
302 # print all we need to make sense of the stats output
303 print "lat_mem_rd with %d iterations, ranges:" % iterations