1 # Copyright (c) 2014-2015, 2017, 2019 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
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11 # modified or unmodified, in source code or in binary form.
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14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
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21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Radhika Jagtap
39 from __future__
import print_function
40 from __future__
import absolute_import
45 from m5
.objects
import *
46 from m5
.util
import addToPath
47 from m5
.stats
import periodicStatDump
51 from common
import MemConfig
53 # This script aims at triggering low power state transitions in the DRAM
54 # controller. The traffic generator is used in DRAM mode and traffic
55 # states target a different levels of bank utilization and strides.
56 # At the end after sweeping through bank utilization and strides, we go
57 # through an idle state with no requests to enforce self-refresh.
59 parser
= argparse
.ArgumentParser(
60 formatter_class
=argparse
.ArgumentDefaultsHelpFormatter
)
62 # Use a single-channel DDR4-2400 in 16x4 configuration by default
63 parser
.add_argument("--mem-type", default
="DDR4_2400_16x4",
64 choices
=MemConfig
.mem_names(),
65 help = "type of memory to use")
67 parser
.add_argument("--mem-ranks", "-r", type=int, default
=1,
68 help = "Number of ranks to iterate across")
70 parser
.add_argument("--page-policy", "-p",
71 choices
=["close_adaptive", "open_adaptive"],
72 default
="close_adaptive", help="controller page policy")
74 parser
.add_argument("--itt-list", "-t", default
="1 20 100",
75 help="a list of multipliers for the max value of itt, " \
78 parser
.add_argument("--rd-perc", type=int, default
=100,
79 help = "Percentage of read commands")
81 parser
.add_argument("--addr-map",
82 choices
=m5
.objects
.AddrMap
.vals
,
83 default
="RoRaBaCoCh", help = "DRAM address map policy")
85 parser
.add_argument("--idle-end", type=int, default
=50000000,
86 help = "time in ps of an idle period at the end ")
88 args
= parser
.parse_args()
90 # Start with the system itself, using a multi-layer 2.0 GHz
91 # crossbar, delivering 64 bytes / 3 cycles (one header cycle)
92 # which amounts to 42.7 GByte/s per layer and thus per port.
93 system
= System(membus
= IOXBar(width
= 32))
94 system
.clk_domain
= SrcClockDomain(clock
= '2.0GHz',
96 VoltageDomain(voltage
= '1V'))
98 # We are fine with 256 MB memory for now.
99 mem_range
= AddrRange('256MB')
101 system
.mem_ranges
= [mem_range
]
103 # Do not worry about reserving space for the backing store
104 system
.mmap_using_noreserve
= True
106 # Force a single channel to match the assumptions in the DRAM traffic
108 args
.mem_channels
= 1
109 args
.external_memory_system
= 0
111 args
.elastic_trace_en
= 0
112 MemConfig
.config_mem(args
, system
)
114 # Sanity check for memory controller class.
115 if not isinstance(system
.mem_ctrls
[0], m5
.objects
.DRAMCtrl
):
116 fatal("This script assumes the memory is a DRAMCtrl subclass")
118 # There is no point slowing things down by saving any data.
119 system
.mem_ctrls
[0].null
= True
121 # Set the address mapping based on input argument
122 system
.mem_ctrls
[0].addr_mapping
= args
.addr_map
123 system
.mem_ctrls
[0].page_policy
= args
.page_policy
125 # We create a traffic generator state for each param combination we want to
126 # test. Each traffic generator state is specified in the config file and the
127 # generator remains in the state for specific period. This period is 0.25 ms.
128 # Stats are dumped and reset at the state transition.
131 # We specify the states in a config file input to the traffic generator.
132 cfg_file_name
= "configs/dram/lowp_sweep.cfg"
133 cfg_file
= open(cfg_file_name
, 'w')
135 # Get the number of banks
136 nbr_banks
= int(system
.mem_ctrls
[0].banks_per_rank
.value
)
138 # determine the burst size in bytes
139 burst_size
= int((system
.mem_ctrls
[0].devices_per_rank
.value
*
140 system
.mem_ctrls
[0].device_bus_width
.value
*
141 system
.mem_ctrls
[0].burst_length
.value
) / 8)
143 # next, get the page size in bytes (the rowbuffer size is already in bytes)
144 page_size
= system
.mem_ctrls
[0].devices_per_rank
.value
* \
145 system
.mem_ctrls
[0].device_rowbuffer_size
.value
147 # Inter-request delay should be such that we can hit as many transitions
148 # to/from low power states as possible to. We provide a min and max itt to the
149 # traffic generator and it randomises in the range. The parameter is in
150 # seconds and we need it in ticks (ps).
151 itt_min
= system
.mem_ctrls
[0].tBURST
.value
* 1000000000000
153 #The itt value when set to (tRAS + tRP + tCK) covers the case where
154 # a read command is delayed beyond the delay from ACT to PRE_PDN entry of the
155 # previous command. For write command followed by precharge, this delay
156 # between a write and power down entry will be tRCD + tCL + tWR + tRP + tCK.
157 # As we use this delay as a unit and create multiples of it as bigger delays
158 # for the sweep, this parameter works for reads, writes and mix of them.
159 pd_entry_time
= (system
.mem_ctrls
[0].tRAS
.value
+
160 system
.mem_ctrls
[0].tRP
.value
+
161 system
.mem_ctrls
[0].tCK
.value
) * 1000000000000
163 # We sweep itt max using the multipliers specified by the user.
164 itt_max_str
= args
.itt_list
.strip().split()
165 itt_max_multiples
= [ int(x
) for x
in itt_max_str
]
166 if len(itt_max_multiples
) == 0:
167 fatal("String for itt-max-list detected empty\n")
169 itt_max_values
= [ pd_entry_time
* m
for m
in itt_max_multiples
]
171 # Generate request addresses in the entire range, assume we start at 0
172 max_addr
= mem_range
.end
174 # For max stride, use min of the page size and 512 bytes as that should be
176 max_stride
= min(512, page_size
)
177 mid_stride
= 4 * burst_size
178 stride_values
= [burst_size
, mid_stride
, max_stride
]
180 # be selective about bank utilization instead of going from 1 to the number of
182 bank_util_values
= [1, int(nbr_banks
/2), nbr_banks
]
184 # Next we create the config file, but first a comment
185 cfg_file
.write("""# STATE state# period mode=DRAM
186 # read_percent start_addr end_addr req_size min_itt max_itt data_limit
187 # stride_size page_size #banks #banks_util addr_map #ranks\n""")
189 addr_map
= m5
.objects
.AddrMap
.map[args
.addr_map
]
192 for itt_max
in itt_max_values
:
193 for bank
in bank_util_values
:
194 for stride_size
in stride_values
:
195 cfg_file
.write("STATE %d %d %s %d 0 %d %d "
196 "%d %d %d %d %d %d %d %d %d\n" %
197 (nxt_state
, period
, "DRAM", args
.rd_perc
, max_addr
,
198 burst_size
, itt_min
, itt_max
, 0, stride_size
,
199 page_size
, nbr_banks
, bank
, addr_map
,
201 nxt_state
= nxt_state
+ 1
203 # State for idle period
204 idle_period
= args
.idle_end
205 cfg_file
.write("STATE %d %d IDLE\n" % (nxt_state
, idle_period
))
207 # Init state is state 0
208 cfg_file
.write("INIT 0\n")
210 # Go through the states one by one
211 for state
in range(1, nxt_state
+ 1):
212 cfg_file
.write("TRANSITION %d %d 1\n" % (state
- 1, state
))
214 # Transition from last state to itself to not break the probability math
215 cfg_file
.write("TRANSITION %d %d 1\n" % (nxt_state
, nxt_state
))
218 # create a traffic generator, and point it to the file we just created
219 system
.tgen
= TrafficGen(config_file
= cfg_file_name
)
221 # add a communication monitor
222 system
.monitor
= CommMonitor()
224 # connect the traffic generator to the bus via a communication monitor
225 system
.tgen
.port
= system
.monitor
.slave
226 system
.monitor
.master
= system
.membus
.slave
228 # connect the system port even if it is not used in this example
229 system
.system_port
= system
.membus
.slave
231 # every period, dump and reset all stats
232 periodicStatDump(period
)
234 root
= Root(full_system
= False, system
= system
)
235 root
.system
.mem_mode
= 'timing'
239 # Simulate for exactly as long as it takes to go through all the states
240 # This is why sim exists.
241 m5
.simulate(nxt_state
* period
+ idle_period
)
242 print("--- Done DRAM low power sweep ---")
243 print("Fixed params - ")
244 print("\tburst: %d, banks: %d, max stride: %d, itt min: %s ns" % \
245 (burst_size
, nbr_banks
, max_stride
, itt_min
))
246 print("Swept params - ")
247 print("\titt max multiples input:", itt_max_multiples
)
248 print("\titt max values", itt_max_values
)
249 print("\tbank utilization values", bank_util_values
)
250 print("\tstride values:", stride_values
)
251 print("Traffic gen config file:", cfg_file_name
)