configs/dram/sweep.py

   1 # Copyright (c) 2014-2015 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Redistribution and use in source and binary forms, with or without
  14 # modification, are permitted provided that the following conditions are
  15 # met: redistributions of source code must retain the above copyright
  16 # notice, this list of conditions and the following disclaimer;
  17 # redistributions in binary form must reproduce the above copyright
  18 # notice, this list of conditions and the following disclaimer in the
  19 # documentation and/or other materials provided with the distribution;
  20 # neither the name of the copyright holders nor the names of its
  21 # contributors may be used to endorse or promote products derived from
  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Andreas Hansson
  37
  38 import optparse
  39
  40 import m5
  41 from m5.objects import *
  42 from m5.util import addToPath
  43 from m5.internal.stats import periodicStatDump
  44
  45 addToPath('../common')
  46
  47 import MemConfig
  48
  49 # this script is helpful to sweep the efficiency of a specific memory
  50 # controller configuration, by varying the number of banks accessed,
  51 # and the sequential stride size (how many bytes per activate), and
  52 # observe what bus utilisation (bandwidth) is achieved
  53
  54 parser = optparse.OptionParser()
  55
  56 # Use a single-channel DDR3-1600 x64 by default
  57 parser.add_option("--mem-type", type="choice", default="ddr3_1600_x64",
  58                   choices=MemConfig.mem_names(),
  59                   help = "type of memory to use")
  60
  61 parser.add_option("--mem-ranks", "-r", type="int", default=1,
  62                   help = "Number of ranks to iterate across")
  63
  64 parser.add_option("--rd_perc", type="int", default=100,
  65                   help = "Percentage of read commands")
  66
  67 parser.add_option("--mode", type="choice", default="DRAM",
  68                   choices=["DRAM", "DRAM_ROTATE"],
  69                   help = "DRAM: Random traffic; \
  70                           DRAM_ROTATE: Traffic rotating across banks and ranks")
  71
  72 parser.add_option("--addr_map", type="int", default=1,
  73                   help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
  74
  75 (options, args) = parser.parse_args()
  76
  77 if args:
  78     print "Error: script doesn't take any positional arguments"
  79     sys.exit(1)
  80
  81 # at the moment we stay with the default open-adaptive page policy,
  82 # and address mapping
  83
  84 # start with the system itself, using a multi-layer 1.5 GHz
  85 # crossbar, delivering 64 bytes / 5 cycles (one header cycle)
  86 # which amounts to 19.2 GByte/s per layer and thus per port
  87 system = System(membus = IOXBar(width = 16))
  88 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
  89                                    voltage_domain =
  90                                    VoltageDomain(voltage = '1V'))
  91
  92 # we are fine with 256 MB memory for now
  93 mem_range = AddrRange('256MB')
  94 system.mem_ranges = [mem_range]
  95
  96 # force a single channel to match the assumptions in the DRAM traffic
  97 # generator
  98 options.mem_channels = 1
  99 MemConfig.config_mem(options, system)
 100
 101 # the following assumes that we are using the native DRAM
 102 # controller, check to be sure
 103 if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
 104     fatal("This script assumes the memory is a DRAMCtrl subclass")
 105
 106 # Set the address mapping based on input argument
 107 # Default to RoRaBaCoCh
 108 if options.addr_map == 0:
 109    system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
 110 elif options.addr_map == 1:
 111    system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
 112 else:
 113     fatal("Did not specify a valid address map argument")
 114
 115 # stay in each state for 0.25 ms, long enough to warm things up, and
 116 # short enough to avoid hitting a refresh
 117 period = 250000000
 118
 119 # this is where we go off piste, and print the traffic generator
 120 # configuration that we will later use, crazy but it works
 121 cfg_file_name = "configs/dram/sweep.cfg"
 122 cfg_file = open(cfg_file_name, 'w')
 123
 124 # stay in each state as long as the dump/reset period, use the entire
 125 # range, issue transactions of the right DRAM burst size, and match
 126 # the DRAM maximum bandwidth to ensure that it is saturated
 127
 128 # get the number of banks
 129 nbr_banks = system.mem_ctrls[0].banks_per_rank.value
 130
 131 # determine the burst length in bytes
 132 burst_size = int((system.mem_ctrls[0].devices_per_rank.value *
 133                   system.mem_ctrls[0].device_bus_width.value *
 134                   system.mem_ctrls[0].burst_length.value) / 8)
 135
 136 # next, get the page size in bytes
 137 page_size = system.mem_ctrls[0].devices_per_rank.value * \
 138     system.mem_ctrls[0].device_rowbuffer_size.value
 139
 140 # match the maximum bandwidth of the memory, the parameter is in ns
 141 # and we need it in ticks
 142 itt = system.mem_ctrls[0].tBURST.value * 1000000000000
 143
 144 # assume we start at 0
 145 max_addr = mem_range.end
 146
 147 # use min of the page size and 512 bytes as that should be more than
 148 # enough
 149 max_stride = min(512, page_size)
 150
 151 # now we create the state by iterating over the stride size from burst
 152 # size to the max stride, and from using only a single bank up to the
 153 # number of banks available
 154 nxt_state = 0
 155 for bank in range(1, nbr_banks + 1):
 156     for stride_size in range(burst_size, max_stride + 1, burst_size):
 157         cfg_file.write("STATE %d %d %s %d 0 %d %d "
 158                        "%d %d %d %d %d %d %d %d %d\n" %
 159                        (nxt_state, period, options.mode, options.rd_perc,
 160                         max_addr, burst_size, itt, itt, 0, stride_size,
 161                         page_size, nbr_banks, bank, options.addr_map,
 162                         options.mem_ranks))
 163         nxt_state = nxt_state + 1
 164
 165 cfg_file.write("INIT 0\n")
 166
 167 # go through the states one by one
 168 for state in range(1, nxt_state):
 169     cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
 170
 171 cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
 172
 173 cfg_file.close()
 174
 175 # create a traffic generator, and point it to the file we just created
 176 system.tgen = TrafficGen(config_file = cfg_file_name)
 177
 178 # add a communication monitor
 179 system.monitor = CommMonitor()
 180
 181 # connect the traffic generator to the bus via a communication monitor
 182 system.tgen.port = system.monitor.slave
 183 system.monitor.master = system.membus.slave
 184
 185 # connect the system port even if it is not used in this example
 186 system.system_port = system.membus.slave
 187
 188 # every period, dump and reset all stats
 189 periodicStatDump(period)
 190
 191 # run Forrest, run!
 192 root = Root(full_system = False, system = system)
 193 root.system.mem_mode = 'timing'
 194
 195 m5.instantiate()
 196 m5.simulate(nxt_state * period)
 197
 198 print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \
 199     (burst_size, nbr_banks, max_stride)