configs/dram/sweep.py

   1 # Copyright (c) 2014-2015, 2018 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Redistribution and use in source and binary forms, with or without
  14 # modification, are permitted provided that the following conditions are
  15 # met: redistributions of source code must retain the above copyright
  16 # notice, this list of conditions and the following disclaimer;
  17 # redistributions in binary form must reproduce the above copyright
  18 # notice, this list of conditions and the following disclaimer in the
  19 # documentation and/or other materials provided with the distribution;
  20 # neither the name of the copyright holders nor the names of its
  21 # contributors may be used to endorse or promote products derived from
  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Andreas Hansson
  37
  38 from __future__ import print_function
  39
  40 import math
  41 import optparse
  42
  43 import m5
  44 from m5.objects import *
  45 from m5.util import addToPath
  46 from m5.stats import periodicStatDump
  47
  48 addToPath('../')
  49
  50 from common import MemConfig
  51
  52 # this script is helpful to sweep the efficiency of a specific memory
  53 # controller configuration, by varying the number of banks accessed,
  54 # and the sequential stride size (how many bytes per activate), and
  55 # observe what bus utilisation (bandwidth) is achieved
  56
  57 parser = optparse.OptionParser()
  58
  59 dram_generators = {
  60     "DRAM" : lambda x: x.createDram,
  61     "DRAM_ROTATE" : lambda x: x.createDramRot,
  62 }
  63
  64 # Use a single-channel DDR3-1600 x64 (8x8 topology) by default
  65 parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
  66                   choices=MemConfig.mem_names(),
  67                   help = "type of memory to use")
  68
  69 parser.add_option("--mem-ranks", "-r", type="int", default=1,
  70                   help = "Number of ranks to iterate across")
  71
  72 parser.add_option("--rd_perc", type="int", default=100,
  73                   help = "Percentage of read commands")
  74
  75 parser.add_option("--mode", type="choice", default="DRAM",
  76                   choices=dram_generators.keys(),
  77                   help = "DRAM: Random traffic; \
  78                           DRAM_ROTATE: Traffic rotating across banks and ranks")
  79
  80 parser.add_option("--addr_map", type="int", default=1,
  81                   help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
  82
  83 (options, args) = parser.parse_args()
  84
  85 if args:
  86     print("Error: script doesn't take any positional arguments")
  87     sys.exit(1)
  88
  89 # at the moment we stay with the default open-adaptive page policy,
  90 # and address mapping
  91
  92 # start with the system itself, using a multi-layer 2.0 GHz
  93 # crossbar, delivering 64 bytes / 3 cycles (one header cycle)
  94 # which amounts to 42.7 GByte/s per layer and thus per port
  95 system = System(membus = IOXBar(width = 32))
  96 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
  97                                    voltage_domain =
  98                                    VoltageDomain(voltage = '1V'))
  99
 100 # we are fine with 256 MB memory for now
 101 mem_range = AddrRange('256MB')
 102 system.mem_ranges = [mem_range]
 103
 104 # do not worry about reserving space for the backing store
 105 system.mmap_using_noreserve = True
 106
 107 # force a single channel to match the assumptions in the DRAM traffic
 108 # generator
 109 options.mem_channels = 1
 110 options.external_memory_system = 0
 111 options.tlm_memory = 0
 112 options.elastic_trace_en = 0
 113 MemConfig.config_mem(options, system)
 114
 115 # the following assumes that we are using the native DRAM
 116 # controller, check to be sure
 117 if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
 118     fatal("This script assumes the memory is a DRAMCtrl subclass")
 119
 120 # there is no point slowing things down by saving any data
 121 system.mem_ctrls[0].null = True
 122
 123 # Set the address mapping based on input argument
 124 # Default to RoRaBaCoCh
 125 if options.addr_map == 0:
 126    system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
 127 elif options.addr_map == 1:
 128    system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
 129 else:
 130     fatal("Did not specify a valid address map argument")
 131
 132 # stay in each state for 0.25 ms, long enough to warm things up, and
 133 # short enough to avoid hitting a refresh
 134 period = 250000000
 135
 136 # stay in each state as long as the dump/reset period, use the entire
 137 # range, issue transactions of the right DRAM burst size, and match
 138 # the DRAM maximum bandwidth to ensure that it is saturated
 139
 140 # get the number of banks
 141 nbr_banks = system.mem_ctrls[0].banks_per_rank.value
 142
 143 # determine the burst length in bytes
 144 burst_size = int((system.mem_ctrls[0].devices_per_rank.value *
 145                   system.mem_ctrls[0].device_bus_width.value *
 146                   system.mem_ctrls[0].burst_length.value) / 8)
 147
 148 # next, get the page size in bytes
 149 page_size = system.mem_ctrls[0].devices_per_rank.value * \
 150     system.mem_ctrls[0].device_rowbuffer_size.value
 151
 152 # match the maximum bandwidth of the memory, the parameter is in seconds
 153 # and we need it in ticks (ps)
 154 itt = system.mem_ctrls[0].tBURST.value * 1000000000000
 155
 156 # assume we start at 0
 157 max_addr = mem_range.end
 158
 159 # use min of the page size and 512 bytes as that should be more than
 160 # enough
 161 max_stride = min(512, page_size)
 162
 163 # create a traffic generator, and point it to the file we just created
 164 system.tgen = PyTrafficGen()
 165
 166 # add a communication monitor
 167 system.monitor = CommMonitor()
 168
 169 # connect the traffic generator to the bus via a communication monitor
 170 system.tgen.port = system.monitor.slave
 171 system.monitor.master = system.membus.slave
 172
 173 # connect the system port even if it is not used in this example
 174 system.system_port = system.membus.slave
 175
 176 # every period, dump and reset all stats
 177 periodicStatDump(period)
 178
 179 # run Forrest, run!
 180 root = Root(full_system = False, system = system)
 181 root.system.mem_mode = 'timing'
 182
 183 m5.instantiate()
 184
 185 def trace():
 186     generator = dram_generators[options.mode](system.tgen)
 187     for bank in range(1, nbr_banks + 1):
 188         for stride_size in range(burst_size, max_stride + 1, burst_size):
 189             num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
 190             yield generator(period,
 191                             0, max_addr, burst_size, int(itt), int(itt),
 192                             options.rd_perc, 0,
 193                             num_seq_pkts, page_size, nbr_banks, bank,
 194                             options.addr_map, options.mem_ranks)
 195     yield system.tgen.createExit(0)
 196
 197 system.tgen.start(trace())
 198
 199 m5.simulate()
 200
 201 print("DRAM sweep with burst: %d, banks: %d, max stride: %d" %
 202     (burst_size, nbr_banks, max_stride))