1 # Copyright (c) 2014-2015 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Hansson
41 from m5
.objects
import *
42 from m5
.util
import addToPath
43 from m5
.internal
.stats
import periodicStatDump
45 addToPath('../common')
49 # this script is helpful to sweep the efficiency of a specific memory
50 # controller configuration, by varying the number of banks accessed,
51 # and the sequential stride size (how many bytes per activate), and
52 # observe what bus utilisation (bandwidth) is achieved
54 parser
= optparse
.OptionParser()
56 # Use a single-channel DDR3-1600 x64 by default
57 parser
.add_option("--mem-type", type="choice", default
="DDR3_1600_x64",
58 choices
=MemConfig
.mem_names(),
59 help = "type of memory to use")
61 parser
.add_option("--mem-ranks", "-r", type="int", default
=1,
62 help = "Number of ranks to iterate across")
64 parser
.add_option("--rd_perc", type="int", default
=100,
65 help = "Percentage of read commands")
67 parser
.add_option("--mode", type="choice", default
="DRAM",
68 choices
=["DRAM", "DRAM_ROTATE"],
69 help = "DRAM: Random traffic; \
70 DRAM_ROTATE: Traffic rotating across banks and ranks")
72 parser
.add_option("--addr_map", type="int", default
=1,
73 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
75 (options
, args
) = parser
.parse_args()
78 print "Error: script doesn't take any positional arguments"
81 # at the moment we stay with the default open-adaptive page policy,
84 # start with the system itself, using a multi-layer 2.0 GHz
85 # crossbar, delivering 64 bytes / 3 cycles (one header cycle)
86 # which amounts to 42.7 GByte/s per layer and thus per port
87 system
= System(membus
= IOXBar(width
= 32))
88 system
.clk_domain
= SrcClockDomain(clock
= '2.0GHz',
90 VoltageDomain(voltage
= '1V'))
92 # we are fine with 256 MB memory for now
93 mem_range
= AddrRange('256MB')
94 system
.mem_ranges
= [mem_range
]
96 # do not worry about reserving space for the backing store
97 system
.mmap_using_noreserve
= True
99 # force a single channel to match the assumptions in the DRAM traffic
101 options
.mem_channels
= 1
102 options
.external_memory_system
= 0
103 options
.tlm_memory
= 0
104 MemConfig
.config_mem(options
, system
)
106 # the following assumes that we are using the native DRAM
107 # controller, check to be sure
108 if not isinstance(system
.mem_ctrls
[0], m5
.objects
.DRAMCtrl
):
109 fatal("This script assumes the memory is a DRAMCtrl subclass")
111 # there is no point slowing things down by saving any data
112 system
.mem_ctrls
[0].null
= True
114 # Set the address mapping based on input argument
115 # Default to RoRaBaCoCh
116 if options
.addr_map
== 0:
117 system
.mem_ctrls
[0].addr_mapping
= "RoCoRaBaCh"
118 elif options
.addr_map
== 1:
119 system
.mem_ctrls
[0].addr_mapping
= "RoRaBaCoCh"
121 fatal("Did not specify a valid address map argument")
123 # stay in each state for 0.25 ms, long enough to warm things up, and
124 # short enough to avoid hitting a refresh
127 # this is where we go off piste, and print the traffic generator
128 # configuration that we will later use, crazy but it works
129 cfg_file_name
= "configs/dram/sweep.cfg"
130 cfg_file
= open(cfg_file_name
, 'w')
132 # stay in each state as long as the dump/reset period, use the entire
133 # range, issue transactions of the right DRAM burst size, and match
134 # the DRAM maximum bandwidth to ensure that it is saturated
136 # get the number of banks
137 nbr_banks
= system
.mem_ctrls
[0].banks_per_rank
.value
139 # determine the burst length in bytes
140 burst_size
= int((system
.mem_ctrls
[0].devices_per_rank
.value
*
141 system
.mem_ctrls
[0].device_bus_width
.value
*
142 system
.mem_ctrls
[0].burst_length
.value
) / 8)
144 # next, get the page size in bytes
145 page_size
= system
.mem_ctrls
[0].devices_per_rank
.value
* \
146 system
.mem_ctrls
[0].device_rowbuffer_size
.value
148 # match the maximum bandwidth of the memory, the parameter is in seconds
149 # and we need it in ticks (ps)
150 itt
= system
.mem_ctrls
[0].tBURST
.value
* 1000000000000
152 # assume we start at 0
153 max_addr
= mem_range
.end
155 # use min of the page size and 512 bytes as that should be more than
157 max_stride
= min(512, page_size
)
159 # now we create the state by iterating over the stride size from burst
160 # size to the max stride, and from using only a single bank up to the
161 # number of banks available
163 for bank
in range(1, nbr_banks
+ 1):
164 for stride_size
in range(burst_size
, max_stride
+ 1, burst_size
):
165 cfg_file
.write("STATE %d %d %s %d 0 %d %d "
166 "%d %d %d %d %d %d %d %d %d\n" %
167 (nxt_state
, period
, options
.mode
, options
.rd_perc
,
168 max_addr
, burst_size
, itt
, itt
, 0, stride_size
,
169 page_size
, nbr_banks
, bank
, options
.addr_map
,
171 nxt_state
= nxt_state
+ 1
173 cfg_file
.write("INIT 0\n")
175 # go through the states one by one
176 for state
in range(1, nxt_state
):
177 cfg_file
.write("TRANSITION %d %d 1\n" % (state
- 1, state
))
179 cfg_file
.write("TRANSITION %d %d 1\n" % (nxt_state
- 1, nxt_state
- 1))
183 # create a traffic generator, and point it to the file we just created
184 system
.tgen
= TrafficGen(config_file
= cfg_file_name
)
186 # add a communication monitor
187 system
.monitor
= CommMonitor()
189 # connect the traffic generator to the bus via a communication monitor
190 system
.tgen
.port
= system
.monitor
.slave
191 system
.monitor
.master
= system
.membus
.slave
193 # connect the system port even if it is not used in this example
194 system
.system_port
= system
.membus
.slave
196 # every period, dump and reset all stats
197 periodicStatDump(period
)
200 root
= Root(full_system
= False, system
= system
)
201 root
.system
.mem_mode
= 'timing'
204 m5
.simulate(nxt_state
* period
)
206 print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \
207 (burst_size
, nbr_banks
, max_stride
)