configs/dram/sweep.py

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  35
  36 from __future__ import print_function
  37 from __future__ import absolute_import
  38
  39 import math
  40 import optparse
  41
  42 import m5
  43 from m5.objects import *
  44 from m5.util import addToPath
  45 from m5.stats import periodicStatDump
  46
  47 addToPath('../')
  48
  49 from common import ObjectList
  50 from common import MemConfig
  51
  52 # this script is helpful to sweep the efficiency of a specific memory
  53 # controller configuration, by varying the number of banks accessed,
  54 # and the sequential stride size (how many bytes per activate), and
  55 # observe what bus utilisation (bandwidth) is achieved
  56
  57 parser = optparse.OptionParser()
  58
  59 dram_generators = {
  60     "DRAM" : lambda x: x.createDram,
  61     "DRAM_ROTATE" : lambda x: x.createDramRot,
  62 }
  63
  64 # Use a single-channel DDR3-1600 x64 (8x8 topology) by default
  65 parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8",
  66                   choices=ObjectList.mem_list.get_names(),
  67                   help = "type of memory to use")
  68
  69 parser.add_option("--mem-ranks", "-r", type="int", default=1,
  70                   help = "Number of ranks to iterate across")
  71
  72 parser.add_option("--rd_perc", type="int", default=100,
  73                   help = "Percentage of read commands")
  74
  75 parser.add_option("--mode", type="choice", default="DRAM",
  76                   choices=dram_generators.keys(),
  77                   help = "DRAM: Random traffic; \
  78                           DRAM_ROTATE: Traffic rotating across banks and ranks")
  79
  80 parser.add_argument("--addr-map",
  81                     choices=m5.objects.AddrMap.vals,
  82                     default="RoRaBaCoCh", help = "DRAM address map policy")
  83
  84 (options, args) = parser.parse_args()
  85
  86 if args:
  87     print("Error: script doesn't take any positional arguments")
  88     sys.exit(1)
  89
  90 # at the moment we stay with the default open-adaptive page policy,
  91 # and address mapping
  92
  93 # start with the system itself, using a multi-layer 2.0 GHz
  94 # crossbar, delivering 64 bytes / 3 cycles (one header cycle)
  95 # which amounts to 42.7 GByte/s per layer and thus per port
  96 system = System(membus = IOXBar(width = 32))
  97 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
  98                                    voltage_domain =
  99                                    VoltageDomain(voltage = '1V'))
 100
 101 # we are fine with 256 MB memory for now
 102 mem_range = AddrRange('256MB')
 103 system.mem_ranges = [mem_range]
 104
 105 # do not worry about reserving space for the backing store
 106 system.mmap_using_noreserve = True
 107
 108 # force a single channel to match the assumptions in the DRAM traffic
 109 # generator
 110 options.mem_channels = 1
 111 options.external_memory_system = 0
 112 options.tlm_memory = 0
 113 options.elastic_trace_en = 0
 114 MemConfig.config_mem(options, system)
 115
 116 # the following assumes that we are using the native DRAM
 117 # controller, check to be sure
 118 if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
 119     fatal("This script assumes the memory is a DRAMCtrl subclass")
 120
 121 # there is no point slowing things down by saving any data
 122 system.mem_ctrls[0].null = True
 123
 124 # Set the address mapping based on input argument
 125 system.mem_ctrls[0].addr_mapping = args.addr_map
 126
 127 # stay in each state for 0.25 ms, long enough to warm things up, and
 128 # short enough to avoid hitting a refresh
 129 period = 250000000
 130
 131 # stay in each state as long as the dump/reset period, use the entire
 132 # range, issue transactions of the right DRAM burst size, and match
 133 # the DRAM maximum bandwidth to ensure that it is saturated
 134
 135 # get the number of banks
 136 nbr_banks = system.mem_ctrls[0].banks_per_rank.value
 137
 138 # determine the burst length in bytes
 139 burst_size = int((system.mem_ctrls[0].devices_per_rank.value *
 140                   system.mem_ctrls[0].device_bus_width.value *
 141                   system.mem_ctrls[0].burst_length.value) / 8)
 142
 143 # next, get the page size in bytes
 144 page_size = system.mem_ctrls[0].devices_per_rank.value * \
 145     system.mem_ctrls[0].device_rowbuffer_size.value
 146
 147 # match the maximum bandwidth of the memory, the parameter is in seconds
 148 # and we need it in ticks (ps)
 149 itt = system.mem_ctrls[0].tBURST.value * 1000000000000
 150
 151 # assume we start at 0
 152 max_addr = mem_range.end
 153
 154 # use min of the page size and 512 bytes as that should be more than
 155 # enough
 156 max_stride = min(512, page_size)
 157
 158 # create a traffic generator, and point it to the file we just created
 159 system.tgen = PyTrafficGen()
 160
 161 # add a communication monitor
 162 system.monitor = CommMonitor()
 163
 164 # connect the traffic generator to the bus via a communication monitor
 165 system.tgen.port = system.monitor.slave
 166 system.monitor.master = system.membus.slave
 167
 168 # connect the system port even if it is not used in this example
 169 system.system_port = system.membus.slave
 170
 171 # every period, dump and reset all stats
 172 periodicStatDump(period)
 173
 174 # run Forrest, run!
 175 root = Root(full_system = False, system = system)
 176 root.system.mem_mode = 'timing'
 177
 178 m5.instantiate()
 179
 180 addr_map = m5.objects.AddrMap.map[args.addr_map]
 181
 182 def trace():
 183     generator = dram_generators[options.mode](system.tgen)
 184     for bank in range(1, nbr_banks + 1):
 185         for stride_size in range(burst_size, max_stride + 1, burst_size):
 186             num_seq_pkts = int(math.ceil(float(stride_size) / burst_size))
 187             yield generator(period,
 188                             0, max_addr, burst_size, int(itt), int(itt),
 189                             options.rd_perc, 0,
 190                             num_seq_pkts, page_size, nbr_banks, bank,
 191                             addr_map, options.mem_ranks)
 192     yield system.tgen.createExit(0)
 193
 194 system.tgen.start(trace())
 195
 196 m5.simulate()
 197
 198 print("DRAM sweep with burst: %d, banks: %d, max stride: %d" %
 199     (burst_size, nbr_banks, max_stride))