configs/dram/sweep.py

   1 # Copyright (c) 2014 ARM Limited
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  35 #
  36 # Authors: Andreas Hansson
  37
  38 import optparse
  39
  40 import m5
  41 from m5.objects import *
  42 from m5.util import addToPath
  43 from m5.internal.stats import periodicStatDump
  44
  45 addToPath('../common')
  46
  47 import MemConfig
  48
  49 # this script is helpful to sweep the efficiency of a specific memory
  50 # controller configuration, by varying the number of banks accessed,
  51 # and the sequential stride size (how many bytes per activate), and
  52 # observe what bus utilisation (bandwidth) is achieved
  53
  54 parser = optparse.OptionParser()
  55
  56 # Use a single-channel DDR3-1600 x64 by default
  57 parser.add_option("--mem-type", type="choice", default="ddr3_1600_x64",
  58                   choices=MemConfig.mem_names(),
  59                   help = "type of memory to use")
  60
  61 parser.add_option("--ranks", "-r", type="int", default=1,
  62                   help = "Number of ranks to iterate across")
  63
  64 parser.add_option("--rd_perc", type="int", default=100,
  65                   help = "Percentage of read commands")
  66
  67 parser.add_option("--mode", type="choice", default="DRAM",
  68                   choices=["DRAM", "DRAM_ROTATE"],
  69                   help = "DRAM: Random traffic; \
  70                           DRAM_ROTATE: Traffic rotating across banks and ranks")
  71
  72 parser.add_option("--addr_map", type="int", default=1,
  73                   help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
  74
  75 (options, args) = parser.parse_args()
  76
  77 if args:
  78     print "Error: script doesn't take any positional arguments"
  79     sys.exit(1)
  80
  81 # at the moment we stay with the default open-adaptive page policy,
  82 # and address mapping
  83
  84 # start with the system itself, using a multi-layer 1.5 GHz
  85 # bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle)
  86 # which amounts to 19.2 GByte/s per layer and thus per port
  87 system = System(membus = NoncoherentBus(width = 16))
  88 system.clk_domain = SrcClockDomain(clock = '1.5GHz',
  89                                    voltage_domain =
  90                                    VoltageDomain(voltage = '1V'))
  91
  92 # we are fine with 256 MB memory for now
  93 mem_range = AddrRange('256MB')
  94 system.mem_ranges = [mem_range]
  95
  96 # force a single channel to match the assumptions in the DRAM traffic
  97 # generator
  98 options.mem_channels = 1
  99 MemConfig.config_mem(options, system)
 100
 101 # the following assumes that we are using the native DRAM
 102 # controller, check to be sure
 103 if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl):
 104     fatal("This script assumes the memory is a DRAMCtrl subclass")
 105
 106 # Set number of ranks based on input argument; default is 1 rank
 107 system.mem_ctrls[0].ranks_per_channel = options.ranks
 108
 109 # Set the address mapping based on input argument
 110 # Default to RoRaBaCoCh
 111 if options.addr_map == 0:
 112    system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh"
 113 elif options.addr_map == 1:
 114    system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh"
 115 else:
 116     fatal("Did not specify a valid address map argument")
 117
 118 # stay in each state for 0.25 ms, long enough to warm things up, and
 119 # short enough to avoid hitting a refresh
 120 period = 250000000
 121
 122 # this is where we go off piste, and print the traffic generator
 123 # configuration that we will later use, crazy but it works
 124 cfg_file_name = "configs/dram/sweep.cfg"
 125 cfg_file = open(cfg_file_name, 'w')
 126
 127 # stay in each state as long as the dump/reset period, use the entire
 128 # range, issue transactions of the right DRAM burst size, and match
 129 # the DRAM maximum bandwidth to ensure that it is saturated
 130
 131 # get the number of banks
 132 nbr_banks = system.mem_ctrls[0].banks_per_rank.value
 133
 134 # determine the burst length in bytes
 135 burst_size = int((system.mem_ctrls[0].devices_per_rank.value *
 136                   system.mem_ctrls[0].device_bus_width.value *
 137                   system.mem_ctrls[0].burst_length.value) / 8)
 138
 139 # next, get the page size in bytes
 140 page_size = system.mem_ctrls[0].devices_per_rank.value * \
 141     system.mem_ctrls[0].device_rowbuffer_size.value
 142
 143 # match the maximum bandwidth of the memory, the parameter is in ns
 144 # and we need it in ticks
 145 itt = system.mem_ctrls[0].tBURST.value * 1000000000000
 146
 147 # assume we start at 0
 148 max_addr = mem_range.end
 149
 150 # use min of the page size and 512 bytes as that should be more than
 151 # enough
 152 max_stride = min(512, page_size)
 153
 154 # now we create the state by iterating over the stride size from burst
 155 # size to the max stride, and from using only a single bank up to the
 156 # number of banks available
 157 nxt_state = 0
 158 for bank in range(1, nbr_banks + 1):
 159     for stride_size in range(burst_size, max_stride + 1, burst_size):
 160         cfg_file.write("STATE %d %d %s %d 0 %d %d "
 161                        "%d %d %d %d %d %d %d %d %d\n" %
 162                        (nxt_state, period, options.mode, options.rd_perc,
 163                         max_addr, burst_size, itt, itt, 0, stride_size,
 164                         page_size, nbr_banks, bank, options.addr_map,
 165                         options.ranks))
 166         nxt_state = nxt_state + 1
 167
 168 cfg_file.write("INIT 0\n")
 169
 170 # go through the states one by one
 171 for state in range(1, nxt_state):
 172     cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state))
 173
 174 cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1))
 175
 176 cfg_file.close()
 177
 178 # create a traffic generator, and point it to the file we just created
 179 system.tgen = TrafficGen(config_file = cfg_file_name)
 180
 181 # add a communication monitor
 182 system.monitor = CommMonitor()
 183
 184 # connect the traffic generator to the bus via a communication monitor
 185 system.tgen.port = system.monitor.slave
 186 system.monitor.master = system.membus.slave
 187
 188 # connect the system port even if it is not used in this example
 189 system.system_port = system.membus.slave
 190
 191 # every period, dump and reset all stats
 192 periodicStatDump(period)
 193
 194 # run Forrest, run!
 195 root = Root(full_system = False, system = system)
 196 root.system.mem_mode = 'timing'
 197
 198 m5.instantiate()
 199 m5.simulate(nxt_state * period)
 200
 201 print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \
 202     (burst_size, nbr_banks, max_stride)