1 # Copyright (c) 2015 Advanced Micro Devices, Inc.
4 # For use for simulation and test purposes only
6 # Redistribution and use in source and binary forms, with or without
7 # modification, are permitted provided that the following conditions are met:
9 # 1. Redistributions of source code must retain the above copyright notice,
10 # this list of conditions and the following disclaimer.
12 # 2. Redistributions in binary form must reproduce the above copyright notice,
13 # this list of conditions and the following disclaimer in the documentation
14 # and/or other materials provided with the distribution.
16 # 3. Neither the name of the copyright holder nor the names of its
17 # contributors may be used to endorse or promote products derived from this
18 # software without specific prior written permission.
20 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 # AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 # IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 # ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
24 # LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 # CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 # SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 # INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 # CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 # ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 # POSSIBILITY OF SUCH DAMAGE.
32 from __future__
import print_function
33 from __future__
import absolute_import
35 import optparse
, os
, re
41 from m5
.objects
import *
42 from m5
.util
import addToPath
48 from common
import Options
49 from common
import Simulation
50 from common
import GPUTLBOptions
, GPUTLBConfig
52 ########################## Script Options ########################
53 def setOption(parser
, opt_str
, value
= 1):
54 # check to make sure the option actually exists
55 if not parser
.has_option(opt_str
):
56 raise Exception("cannot find %s in list of possible options" % opt_str
)
58 opt
= parser
.get_option(opt_str
)
60 exec("parser.values.%s = %s" % (opt
.dest
, value
))
62 def getOption(parser
, opt_str
):
63 # check to make sure the option actually exists
64 if not parser
.has_option(opt_str
):
65 raise Exception("cannot find %s in list of possible options" % opt_str
)
67 opt
= parser
.get_option(opt_str
)
69 exec("return_value = parser.values.%s" % opt
.dest
)
72 # Adding script options
73 parser
= optparse
.OptionParser()
74 Options
.addCommonOptions(parser
)
75 Options
.addSEOptions(parser
)
77 parser
.add_option("--cpu-only-mode", action
="store_true", default
=False,
78 help="APU mode. Used to take care of problems in "\
79 "Ruby.py while running APU protocols")
80 parser
.add_option("-k", "--kernel-files",
81 help="file(s) containing GPU kernel code (colon separated)")
82 parser
.add_option("-u", "--num-compute-units", type="int", default
=1,
83 help="number of GPU compute units"),
84 parser
.add_option("--num-cp", type="int", default
=0,
85 help="Number of GPU Command Processors (CP)")
86 parser
.add_option("--benchmark-root", help="Root of benchmark directory tree")
88 # not super important now, but to avoid putting the number 4 everywhere, make
90 parser
.add_option("--cu-per-sqc", type="int", default
=4, help="number of CUs" \
91 "sharing an SQC (icache, and thus icache TLB)")
92 parser
.add_option("--simds-per-cu", type="int", default
=4, help="SIMD units" \
94 parser
.add_option("--wf-size", type="int", default
=64,
95 help="Wavefront size(in workitems)")
96 parser
.add_option("--sp-bypass-path-length", type="int", default
=4, \
97 help="Number of stages of bypass path in vector ALU for Single Precision ops")
98 parser
.add_option("--dp-bypass-path-length", type="int", default
=4, \
99 help="Number of stages of bypass path in vector ALU for Double Precision ops")
100 # issue period per SIMD unit: number of cycles before issuing another vector
101 parser
.add_option("--issue-period", type="int", default
=4, \
102 help="Number of cycles per vector instruction issue period")
103 parser
.add_option("--glbmem-wr-bus-width", type="int", default
=32, \
104 help="VGPR to Coalescer (Global Memory) data bus width in bytes")
105 parser
.add_option("--glbmem-rd-bus-width", type="int", default
=32, \
106 help="Coalescer to VGPR (Global Memory) data bus width in bytes")
107 # Currently we only support 1 local memory pipe
108 parser
.add_option("--shr-mem-pipes-per-cu", type="int", default
=1, \
109 help="Number of Shared Memory pipelines per CU")
110 # Currently we only support 1 global memory pipe
111 parser
.add_option("--glb-mem-pipes-per-cu", type="int", default
=1, \
112 help="Number of Global Memory pipelines per CU")
113 parser
.add_option("--wfs-per-simd", type="int", default
=10, help="Number of " \
116 parser
.add_option("--vreg-file-size", type="int", default
=2048,
117 help="number of physical vector registers per SIMD")
118 parser
.add_option("--bw-scalor", type="int", default
=0,
119 help="bandwidth scalor for scalability analysis")
120 parser
.add_option("--CPUClock", type="string", default
="2GHz",
122 parser
.add_option("--GPUClock", type="string", default
="1GHz",
124 parser
.add_option("--cpu-voltage", action
="store", type="string",
126 help = """CPU voltage domain""")
127 parser
.add_option("--gpu-voltage", action
="store", type="string",
129 help = """CPU voltage domain""")
130 parser
.add_option("--CUExecPolicy", type="string", default
="OLDEST-FIRST",
131 help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)")
132 parser
.add_option("--xact-cas-mode", action
="store_true",
133 help="enable load_compare mode (transactional CAS)")
134 parser
.add_option("--SegFaultDebug",action
="store_true",
135 help="checks for GPU seg fault before TLB access")
136 parser
.add_option("--FunctionalTLB",action
="store_true",
137 help="Assumes TLB has no latency")
138 parser
.add_option("--LocalMemBarrier",action
="store_true",
139 help="Barrier does not wait for writethroughs to complete")
140 parser
.add_option("--countPages", action
="store_true",
141 help="Count Page Accesses and output in per-CU output files")
142 parser
.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\
144 parser
.add_option("--pf-type", type="string", help="type of prefetch: "\
145 "PF_CU, PF_WF, PF_PHASE, PF_STRIDE")
146 parser
.add_option("--pf-stride", type="int", help="set prefetch stride")
147 parser
.add_option("--numLdsBanks", type="int", default
=32,
148 help="number of physical banks per LDS module")
149 parser
.add_option("--ldsBankConflictPenalty", type="int", default
=1,
150 help="number of cycles per LDS bank conflict")
151 parser
.add_option('--fast-forward-pseudo-op', action
='store_true',
152 help = 'fast forward using kvm until the m5_switchcpu'
153 ' pseudo-op is encountered, then switch cpus. subsequent'
154 ' m5_switchcpu pseudo-ops will toggle back and forth')
155 parser
.add_option('--outOfOrderDataDelivery', action
='store_true',
156 default
=False, help='enable OoO data delivery in the GM'
159 Ruby
.define_options(parser
)
161 #add TLB options to the parser
162 GPUTLBOptions
.tlb_options(parser
)
164 (options
, args
) = parser
.parse_args()
166 # The GPU cache coherence protocols only work with the backing store
167 setOption(parser
, "--access-backing-store")
169 # if benchmark root is specified explicitly, that overrides the search path
170 if options
.benchmark_root
:
171 benchmark_path
= [options
.benchmark_root
]
173 # Set default benchmark search path to current dir
174 benchmark_path
= ['.']
176 ########################## Sanity Check ########################
178 # Currently the gpu model requires ruby
179 if buildEnv
['PROTOCOL'] == 'None':
180 fatal("GPU model requires ruby")
182 # Currently the gpu model requires only timing or detailed CPU
183 if not (options
.cpu_type
== "TimingSimpleCPU" or
184 options
.cpu_type
== "DerivO3CPU"):
185 fatal("GPU model requires TimingSimpleCPU or DerivO3CPU")
187 # This file can support multiple compute units
188 assert(options
.num_compute_units
>= 1)
190 # Currently, the sqc (I-Cache of GPU) is shared by
191 # multiple compute units(CUs). The protocol works just fine
192 # even if sqc is not shared. Overriding this option here
193 # so that the user need not explicitly set this (assuming
194 # sharing sqc is the common usage)
195 n_cu
= options
.num_compute_units
196 num_sqc
= int(math
.ceil(float(n_cu
) / options
.cu_per_sqc
))
197 options
.num_sqc
= num_sqc
# pass this to Ruby
199 ########################## Creating the GPU system ########################
201 shader
= Shader(n_wf
= options
.wfs_per_simd
,
202 clk_domain
= SrcClockDomain(
203 clock
= options
.GPUClock
,
204 voltage_domain
= VoltageDomain(
205 voltage
= options
.gpu_voltage
)))
207 # GPU_RfO(Read For Ownership) implements SC/TSO memory model.
208 # Other GPU protocols implement release consistency at GPU side.
209 # So, all GPU protocols other than GPU_RfO should make their writes
210 # visible to the global memory and should read from global memory
211 # during kernal boundary. The pipeline initiates(or do not initiate)
212 # the acquire/release operation depending on this impl_kern_boundary_sync
213 # flag. This flag=true means pipeline initiates a acquire/release operation
214 # at kernel boundary.
215 if buildEnv
['PROTOCOL'] == 'GPU_RfO':
216 shader
.impl_kern_boundary_sync
= False
218 shader
.impl_kern_boundary_sync
= True
220 # Switching off per-lane TLB by default
222 if options
.TLB_config
== "perLane":
225 # List of compute units; one GPU can have multiple compute units
227 for i
in range(n_cu
):
228 compute_units
.append(ComputeUnit(cu_id
= i
, perLaneTLB
= per_lane
,
229 num_SIMDs
= options
.simds_per_cu
,
230 wfSize
= options
.wf_size
,
231 spbypass_pipe_length
= options
.sp_bypass_path_length
,
232 dpbypass_pipe_length
= options
.dp_bypass_path_length
,
233 issue_period
= options
.issue_period
,
234 coalescer_to_vrf_bus_width
= \
235 options
.glbmem_rd_bus_width
,
236 vrf_to_coalescer_bus_width
= \
237 options
.glbmem_wr_bus_width
,
238 num_global_mem_pipes
= \
239 options
.glb_mem_pipes_per_cu
,
240 num_shared_mem_pipes
= \
241 options
.shr_mem_pipes_per_cu
,
242 n_wf
= options
.wfs_per_simd
,
243 execPolicy
= options
.CUExecPolicy
,
244 xactCasMode
= options
.xact_cas_mode
,
245 debugSegFault
= options
.SegFaultDebug
,
246 functionalTLB
= options
.FunctionalTLB
,
247 localMemBarrier
= options
.LocalMemBarrier
,
248 countPages
= options
.countPages
,
250 LdsState(banks
= options
.numLdsBanks
,
251 bankConflictPenalty
= \
252 options
.ldsBankConflictPenalty
),
253 out_of_order_data_delivery
=
254 options
.outOfOrderDataDelivery
))
257 for j
in range(options
.simds_per_cu
):
258 for k
in range(shader
.n_wf
):
259 wavefronts
.append(Wavefront(simdId
= j
, wf_slot_id
= k
,
260 wfSize
= options
.wf_size
))
261 vrfs
.append(VectorRegisterFile(simd_id
=j
,
262 num_regs_per_simd
=options
.vreg_file_size
))
263 compute_units
[-1].wavefronts
= wavefronts
264 compute_units
[-1].vector_register_file
= vrfs
265 if options
.TLB_prefetch
:
266 compute_units
[-1].prefetch_depth
= options
.TLB_prefetch
267 compute_units
[-1].prefetch_prev_type
= options
.pf_type
269 # attach the LDS and the CU to the bus (actually a Bridge)
270 compute_units
[-1].ldsPort
= compute_units
[-1].ldsBus
.slave
271 compute_units
[-1].ldsBus
.master
= compute_units
[-1].localDataStore
.cuPort
273 # Attach compute units to GPU
274 shader
.CUs
= compute_units
276 ########################## Creating the CPU system ########################
277 options
.num_cpus
= options
.num_cpus
279 # The shader core will be whatever is after the CPU cores are accounted for
280 shader_idx
= options
.num_cpus
282 # The command processor will be whatever is after the shader is accounted for
283 cp_idx
= shader_idx
+ 1
289 CpuClass
, mem_mode
= Simulation
.getCPUClass(options
.cpu_type
)
290 if CpuClass
== AtomicSimpleCPU
:
291 fatal("AtomicSimpleCPU is not supported")
292 if mem_mode
!= 'timing':
293 fatal("Only the timing memory mode is supported")
296 if options
.fast_forward
and options
.fast_forward_pseudo_op
:
297 fatal("Cannot fast-forward based both on the number of instructions and"
299 fast_forward
= options
.fast_forward
or options
.fast_forward_pseudo_op
302 FutureCpuClass
, future_mem_mode
= CpuClass
, mem_mode
305 mem_mode
= 'atomic_noncaching'
306 # Leave shader.timing untouched, because its value only matters at the
307 # start of the simulation and because we require switching cpus
308 # *before* the first kernel launch.
312 # Initial CPUs to be used during fast-forwarding.
313 for i
in range(options
.num_cpus
):
314 cpu
= CpuClass(cpu_id
= i
,
315 clk_domain
= SrcClockDomain(
316 clock
= options
.CPUClock
,
317 voltage_domain
= VoltageDomain(
318 voltage
= options
.cpu_voltage
)))
321 if options
.fast_forward
:
322 cpu
.max_insts_any_thread
= int(options
.fast_forward
)
325 MainCpuClass
= FutureCpuClass
327 MainCpuClass
= CpuClass
329 # CPs to be used throughout the simulation.
330 for i
in range(options
.num_cp
):
331 cp
= MainCpuClass(cpu_id
= options
.num_cpus
+ i
,
332 clk_domain
= SrcClockDomain(
333 clock
= options
.CPUClock
,
334 voltage_domain
= VoltageDomain(
335 voltage
= options
.cpu_voltage
)))
338 # Main CPUs (to be used after fast-forwarding if fast-forwarding is specified).
339 for i
in range(options
.num_cpus
):
340 cpu
= MainCpuClass(cpu_id
= i
,
341 clk_domain
= SrcClockDomain(
342 clock
= options
.CPUClock
,
343 voltage_domain
= VoltageDomain(
344 voltage
= options
.cpu_voltage
)))
346 cpu
.switched_out
= True
347 future_cpu_list
.append(cpu
)
351 ########################## Creating the GPU dispatcher ########################
352 # Dispatcher dispatches work from host CPU to GPU
353 host_cpu
= cpu_list
[0]
354 dispatcher
= GpuDispatcher()
356 ########################## Create and assign the workload ########################
357 # Check for rel_path in elements of base_list using test, returning
358 # the first full path that satisfies test
359 def find_path(base_list
, rel_path
, test
):
360 for base
in base_list
:
362 # base could be None if environment var not set
364 full_path
= os
.path
.join(base
, rel_path
)
367 fatal("%s not found in %s" % (rel_path
, base_list
))
369 def find_file(base_list
, rel_path
):
370 return find_path(base_list
, rel_path
, os
.path
.isfile
)
372 executable
= find_path(benchmark_path
, options
.cmd
, os
.path
.exists
)
373 # it's common for a benchmark to be in a directory with the same
374 # name as the executable, so we handle that automatically
375 if os
.path
.isdir(executable
):
376 benchmark_path
= [executable
]
377 executable
= find_file(benchmark_path
, options
.cmd
)
378 if options
.kernel_files
:
379 kernel_files
= [find_file(benchmark_path
, f
)
380 for f
in options
.kernel_files
.split(':')]
382 # if kernel_files is not set, see if there's a unique .asm file
383 # in the same directory as the executable
384 kernel_path
= os
.path
.dirname(executable
)
385 kernel_files
= glob
.glob(os
.path
.join(kernel_path
, '*.asm'))
387 print("Using GPU kernel code file(s)", ",".join(kernel_files
))
389 fatal("Can't locate kernel code (.asm) in " + kernel_path
)
392 driver
= ClDriver(filename
="hsa", codefile
=kernel_files
)
395 cpu
.workload
= Process(executable
= executable
,
396 cmd
= [options
.cmd
] + options
.options
.split(),
399 cp
.workload
= host_cpu
.workload
402 for i
in range(len(future_cpu_list
)):
403 future_cpu_list
[i
].workload
= cpu_list
[i
].workload
404 future_cpu_list
[i
].createThreads()
406 ########################## Create the overall system ########################
407 # List of CPUs that must be switched when moving between KVM and simulation
410 [(cpu_list
[i
], future_cpu_list
[i
]) for i
in range(options
.num_cpus
)]
412 # Full list of processing cores in the system. Note that
413 # dispatcher is also added to cpu_list although it is
414 # not a processing element
415 cpu_list
= cpu_list
+ [shader
] + cp_list
+ [dispatcher
]
417 # creating the overall system
418 # notice the cpu list is explicitly added as a parameter to System
419 system
= System(cpu
= cpu_list
,
420 mem_ranges
= [AddrRange(options
.mem_size
)],
421 cache_line_size
= options
.cacheline_size
,
424 system
.future_cpu
= future_cpu_list
425 system
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
426 system
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
427 voltage_domain
= system
.voltage_domain
)
430 have_kvm_support
= 'BaseKvmCPU' in globals()
431 if have_kvm_support
and buildEnv
['TARGET_ISA'] == "x86":
433 for i
in range(len(host_cpu
.workload
)):
434 host_cpu
.workload
[i
].useArchPT
= True
435 host_cpu
.workload
[i
].kvmInSE
= True
437 fatal("KvmCPU can only be used in SE mode with x86")
439 # configure the TLB hierarchy
440 GPUTLBConfig
.config_tlb_hierarchy(options
, system
, shader_idx
)
443 system
.piobus
= IOXBar(width
=32, response_latency
=0,
444 frontend_latency
=0, forward_latency
=0)
445 Ruby
.create_system(options
, None, system
)
446 system
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
,
447 voltage_domain
= system
.voltage_domain
)
449 # attach the CPU ports to Ruby
450 for i
in range(options
.num_cpus
):
451 ruby_port
= system
.ruby
._cpu
_ports
[i
]
453 # Create interrupt controller
454 system
.cpu
[i
].createInterruptController()
456 # Connect cache port's to ruby
457 system
.cpu
[i
].icache_port
= ruby_port
.slave
458 system
.cpu
[i
].dcache_port
= ruby_port
.slave
460 ruby_port
.mem_master_port
= system
.piobus
.slave
461 if buildEnv
['TARGET_ISA'] == "x86":
462 system
.cpu
[i
].interrupts
[0].pio
= system
.piobus
.master
463 system
.cpu
[i
].interrupts
[0].int_master
= system
.piobus
.slave
464 system
.cpu
[i
].interrupts
[0].int_slave
= system
.piobus
.master
466 system
.cpu
[i
].itb
.walker
.port
= ruby_port
.slave
467 system
.cpu
[i
].dtb
.walker
.port
= ruby_port
.slave
469 # attach CU ports to Ruby
470 # Because of the peculiarities of the CP core, you may have 1 CPU but 2
471 # sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be
472 # hooked up until after the CP. To make this script generic, figure out
473 # the index as below, but note that this assumes there is one sequencer
474 # per compute unit and one sequencer per SQC for the math to work out
476 gpu_port_idx
= len(system
.ruby
._cpu
_ports
) \
477 - options
.num_compute_units
- options
.num_sqc
478 gpu_port_idx
= gpu_port_idx
- options
.num_cp
* 2
480 wavefront_size
= options
.wf_size
481 for i
in range(n_cu
):
482 # The pipeline issues wavefront_size number of uncoalesced requests
483 # in one GPU issue cycle. Hence wavefront_size mem ports.
484 for j
in range(wavefront_size
):
485 system
.cpu
[shader_idx
].CUs
[i
].memory_port
[j
] = \
486 system
.ruby
._cpu
_ports
[gpu_port_idx
].slave
[j
]
489 for i
in range(n_cu
):
490 if i
> 0 and not i
% options
.cu_per_sqc
:
491 print("incrementing idx on ", i
)
493 system
.cpu
[shader_idx
].CUs
[i
].sqc_port
= \
494 system
.ruby
._cpu
_ports
[gpu_port_idx
].slave
495 gpu_port_idx
= gpu_port_idx
+ 1
497 # attach CP ports to Ruby
498 for i
in range(options
.num_cp
):
499 system
.cpu
[cp_idx
].createInterruptController()
500 system
.cpu
[cp_idx
].dcache_port
= \
501 system
.ruby
._cpu
_ports
[gpu_port_idx
+ i
* 2].slave
502 system
.cpu
[cp_idx
].icache_port
= \
503 system
.ruby
._cpu
_ports
[gpu_port_idx
+ i
* 2 + 1].slave
504 system
.cpu
[cp_idx
].interrupts
[0].pio
= system
.piobus
.master
505 system
.cpu
[cp_idx
].interrupts
[0].int_master
= system
.piobus
.slave
506 system
.cpu
[cp_idx
].interrupts
[0].int_slave
= system
.piobus
.master
509 # connect dispatcher to the system.piobus
510 dispatcher
.pio
= system
.piobus
.master
511 dispatcher
.dma
= system
.piobus
.slave
513 ################# Connect the CPU and GPU via GPU Dispatcher ###################
514 # CPU rings the GPU doorbell to notify a pending task
515 # using this interface.
516 # And GPU uses this interface to notify the CPU of task completion
517 # The communcation happens through emulated driver.
519 # Note this implicit setting of the cpu_pointer, shader_pointer and tlb array
520 # parameters must be after the explicit setting of the System cpu list
522 shader
.cpu_pointer
= future_cpu_list
[0]
523 dispatcher
.cpu
= future_cpu_list
[0]
525 shader
.cpu_pointer
= host_cpu
526 dispatcher
.cpu
= host_cpu
527 dispatcher
.shader_pointer
= shader
528 dispatcher
.cl_driver
= driver
530 ########################## Start simulation ########################
532 root
= Root(system
=system
, full_system
=False)
533 m5
.ticks
.setGlobalFrequency('1THz')
534 if options
.abs_max_tick
:
535 maxtick
= options
.abs_max_tick
539 # Benchmarks support work item annotations
540 Simulation
.setWorkCountOptions(system
, options
)
542 # Checkpointing is not supported by APU model
543 if (options
.checkpoint_dir
!= None or
544 options
.checkpoint_restore
!= None):
545 fatal("Checkpointing not supported by apu model")
547 checkpoint_dir
= None
548 m5
.instantiate(checkpoint_dir
)
550 # Map workload to this address space
551 host_cpu
.workload
[0].map(0x10000000, 0x200000000, 4096)
553 if options
.fast_forward
:
554 print("Switch at instruction count: %d" % cpu_list
[0].max_insts_any_thread
)
556 exit_event
= m5
.simulate(maxtick
)
558 if options
.fast_forward
:
559 if exit_event
.getCause() == "a thread reached the max instruction count":
560 m5
.switchCpus(system
, switch_cpu_list
)
561 print("Switched CPUS @ tick %s" % (m5
.curTick()))
563 exit_event
= m5
.simulate(maxtick
- m5
.curTick())
564 elif options
.fast_forward_pseudo_op
:
565 while exit_event
.getCause() == "switchcpu":
566 # If we are switching *to* kvm, then the current stats are meaningful
567 # Note that we don't do any warmup by default
568 if type(switch_cpu_list
[0][0]) == FutureCpuClass
:
569 print("Dumping stats...")
571 m5
.switchCpus(system
, switch_cpu_list
)
572 print("Switched CPUS @ tick %s" % (m5
.curTick()))
574 # This lets us switch back and forth without keeping a counter
575 switch_cpu_list
= [(x
[1], x
[0]) for x
in switch_cpu_list
]
576 exit_event
= m5
.simulate(maxtick
- m5
.curTick())
578 print("Ticks:", m5
.curTick())
579 print('Exiting because ', exit_event
.getCause())
580 sys
.exit(exit_event
.getCode())