0c08ea23d3d56ac205900f4dcdf1a47aac3811ba
1 # Copyright (c) 2016-2017 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
39 # System components used by the bigLITTLE.py configuration script
42 from m5
.objects
import *
43 m5
.util
.addToPath('../../')
44 from common
.Caches
import *
45 from common
import CpuConfig
47 have_kvm
= "ArmV8KvmCPU" in CpuConfig
.cpu_names()
70 class WalkCache(PageTableWalkerCache
):
90 clusivity
='mostly_excl'
101 clusivity
='mostly_excl'
104 class MemBus(SystemXBar
):
105 badaddr_responder
= BadAddr(warn_access
="warn")
106 default
= Self
.badaddr_responder
.pio
109 class CpuCluster(SubSystem
):
110 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
,
111 cpu_type
, l1i_type
, l1d_type
, wcache_type
, l2_type
):
112 super(CpuCluster
, self
).__init
__()
113 self
._cpu
_type
= cpu_type
114 self
._l1i
_type
= l1i_type
115 self
._l1d
_type
= l1d_type
116 self
._wcache
_type
= wcache_type
117 self
._l2_type
= l2_type
121 self
.voltage_domain
= VoltageDomain(voltage
=cpu_voltage
)
122 self
.clk_domain
= SrcClockDomain(clock
=cpu_clock
,
123 voltage_domain
=self
.voltage_domain
)
125 self
.cpus
= [ self
._cpu
_type
(cpu_id
=system
.numCpus() + idx
,
126 clk_domain
=self
.clk_domain
)
127 for idx
in range(num_cpus
) ]
129 for cpu
in self
.cpus
:
131 cpu
.createInterruptController()
132 cpu
.socket_id
= system
.numCpuClusters()
133 system
.addCpuCluster(self
, num_cpus
)
135 def requireCaches(self
):
136 return self
._cpu
_type
.require_caches()
138 def memoryMode(self
):
139 return self
._cpu
_type
.memory_mode()
142 for cpu
in self
.cpus
:
143 l1i
= None if self
._l1i
_type
is None else self
._l1i
_type
()
144 l1d
= None if self
._l1d
_type
is None else self
._l1d
_type
()
145 iwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
146 dwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
147 cpu
.addPrivateSplitL1Caches(l1i
, l1d
, iwc
, dwc
)
149 def addL2(self
, clk_domain
):
150 if self
._l2_type
is None:
152 self
.toL2Bus
= L2XBar(width
=64, clk_domain
=clk_domain
)
153 self
.l2
= self
._l2_type
()
154 for cpu
in self
.cpus
:
155 cpu
.connectAllPorts(self
.toL2Bus
)
156 self
.toL2Bus
.master
= self
.l2
.cpu_side
158 def connectMemSide(self
, bus
):
161 self
.l2
.mem_side
= bus
.slave
162 except AttributeError:
163 for cpu
in self
.cpus
:
164 cpu
.connectAllPorts(bus
)
167 class AtomicCluster(CpuCluster
):
168 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
169 cpu_config
= [ CpuConfig
.get("AtomicSimpleCPU"), None, None, None, None ]
170 super(AtomicCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
171 cpu_voltage
, *cpu_config
)
175 class KvmCluster(CpuCluster
):
176 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
177 cpu_config
= [ CpuConfig
.get("ArmV8KvmCPU"), None, None, None, None ]
178 super(KvmCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
179 cpu_voltage
, *cpu_config
)
184 class SimpleSystem(LinuxArmSystem
):
187 def __init__(self
, caches
, mem_size
, **kwargs
):
188 super(SimpleSystem
, self
).__init
__(**kwargs
)
190 self
.voltage_domain
= VoltageDomain(voltage
="1.0V")
191 self
.clk_domain
= SrcClockDomain(clock
="1GHz",
192 voltage_domain
=Parent
.voltage_domain
)
194 self
.realview
= VExpress_GEM5_V1()
196 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
197 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
199 self
.membus
= MemBus()
201 self
.intrctrl
= IntrControl()
202 self
.terminal
= Terminal()
203 self
.vncserver
= VncServer()
205 self
.iobus
= IOXBar()
207 self
.iobridge
= Bridge(delay
='50ns')
209 mem_range
= self
.realview
._mem
_regions
[0]
210 assert long(mem_range
.size()) >= long(Addr(mem_size
))
211 self
.mem_ranges
= [ AddrRange(start
=mem_range
.start
, size
=mem_size
) ]
212 self
._caches
= caches
214 self
.iocache
= IOCache(addr_ranges
=[self
.mem_ranges
[0]])
216 self
.dmabridge
= Bridge(delay
='50ns',
217 ranges
=[self
.mem_ranges
[0]])
219 self
._pci
_devices
= 0
223 def attach_pci(self
, dev
):
224 dev
.pci_bus
, dev
.pci_dev
, dev
.pci_func
= (0, self
._pci
_devices
+ 1, 0)
225 self
._pci
_devices
+= 1
226 self
.realview
.attachPciDevice(dev
, self
.iobus
)
229 self
.iobridge
.master
= self
.iobus
.slave
230 self
.iobridge
.slave
= self
.membus
.master
233 self
.iocache
.mem_side
= self
.membus
.slave
234 self
.iocache
.cpu_side
= self
.iobus
.master
236 self
.dmabridge
.master
= self
.membus
.slave
237 self
.dmabridge
.slave
= self
.iobus
.master
239 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
240 self
.realview
.attachOnChipIO(self
.membus
, self
.iobridge
)
241 self
.realview
.attachIO(self
.iobus
)
242 self
.system_port
= self
.membus
.slave
244 def numCpuClusters(self
):
245 return len(self
._clusters
)
247 def addCpuCluster(self
, cpu_cluster
, num_cpus
):
248 assert cpu_cluster
not in self
._clusters
250 self
._clusters
.append(cpu_cluster
)
251 self
._num
_cpus
+= num_cpus
254 return self
._num
_cpus
256 def addCaches(self
, need_caches
, last_cache_level
):
258 # connect each cluster to the memory hierarchy
259 for cluster
in self
._clusters
:
260 cluster
.connectMemSide(self
.membus
)
263 cluster_mem_bus
= self
.membus
264 assert last_cache_level
>= 1 and last_cache_level
<= 3
265 for cluster
in self
._clusters
:
267 if last_cache_level
> 1:
268 for cluster
in self
._clusters
:
269 cluster
.addL2(cluster
.clk_domain
)
270 if last_cache_level
> 2:
271 max_clock_cluster
= max(self
._clusters
,
272 key
=lambda c
: c
.clk_domain
.clock
[0])
273 self
.l3
= L3(clk_domain
=max_clock_cluster
.clk_domain
)
274 self
.toL3Bus
= L2XBar(width
=64)
275 self
.toL3Bus
.master
= self
.l3
.cpu_side
276 self
.l3
.mem_side
= self
.membus
.slave
277 cluster_mem_bus
= self
.toL3Bus
279 # connect each cluster to the memory hierarchy
280 for cluster
in self
._clusters
:
281 cluster
.connectMemSide(cluster_mem_bus
)