1 # Copyright (c) 2016-2017, 2019 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
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21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # System components used by the bigLITTLE.py configuration script
38 from __future__
import print_function
39 from __future__
import absolute_import
42 from m5
.objects
import *
43 m5
.util
.addToPath('../../')
44 from common
.Caches
import *
45 from common
import ObjectList
47 have_kvm
= "ArmV8KvmCPU" in ObjectList
.cpu_list
.get_names()
48 have_fastmodel
= "FastModelCortexA76" in ObjectList
.cpu_list
.get_names()
71 class WalkCache(PageTableWalkerCache
):
91 clusivity
='mostly_excl'
102 clusivity
='mostly_excl'
105 class MemBus(SystemXBar
):
106 badaddr_responder
= BadAddr(warn_access
="warn")
107 default
= Self
.badaddr_responder
.pio
110 class CpuCluster(SubSystem
):
111 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
,
112 cpu_type
, l1i_type
, l1d_type
, wcache_type
, l2_type
):
113 super(CpuCluster
, self
).__init
__()
114 self
._cpu
_type
= cpu_type
115 self
._l1i
_type
= l1i_type
116 self
._l1d
_type
= l1d_type
117 self
._wcache
_type
= wcache_type
118 self
._l2_type
= l2_type
122 self
.voltage_domain
= VoltageDomain(voltage
=cpu_voltage
)
123 self
.clk_domain
= SrcClockDomain(clock
=cpu_clock
,
124 voltage_domain
=self
.voltage_domain
)
126 self
.cpus
= [ self
._cpu
_type
(cpu_id
=system
.numCpus() + idx
,
127 clk_domain
=self
.clk_domain
)
128 for idx
in range(num_cpus
) ]
130 for cpu
in self
.cpus
:
132 cpu
.createInterruptController()
133 cpu
.socket_id
= system
.numCpuClusters()
134 system
.addCpuCluster(self
, num_cpus
)
136 def requireCaches(self
):
137 return self
._cpu
_type
.require_caches()
139 def memoryMode(self
):
140 return self
._cpu
_type
.memory_mode()
143 for cpu
in self
.cpus
:
144 l1i
= None if self
._l1i
_type
is None else self
._l1i
_type
()
145 l1d
= None if self
._l1d
_type
is None else self
._l1d
_type
()
146 iwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
147 dwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
148 cpu
.addPrivateSplitL1Caches(l1i
, l1d
, iwc
, dwc
)
150 def addL2(self
, clk_domain
):
151 if self
._l2_type
is None:
153 self
.toL2Bus
= L2XBar(width
=64, clk_domain
=clk_domain
)
154 self
.l2
= self
._l2_type
()
155 for cpu
in self
.cpus
:
156 cpu
.connectAllPorts(self
.toL2Bus
)
157 self
.toL2Bus
.master
= self
.l2
.cpu_side
159 def addPMUs(self
, ints
, events
=[]):
161 Instantiates 1 ArmPMU per PE. The method is accepting a list of
162 interrupt numbers (ints) used by the PMU and a list of events to
165 :param ints: List of interrupt numbers. The code will iterate over
166 the cpu list in order and will assign to every cpu in the cluster
167 a PMU with the matching interrupt.
168 :type ints: List[int]
169 :param events: Additional events to be measured by the PMUs
170 :type events: List[Union[ProbeEvent, SoftwareIncrement]]
172 assert len(ints
) == len(self
.cpus
)
173 for cpu
, pint
in zip(self
.cpus
, ints
):
174 int_cls
= ArmPPI
if pint
< 32 else ArmSPI
176 isa
.pmu
= ArmPMU(interrupt
=int_cls(num
=pint
))
177 isa
.pmu
.addArchEvents(cpu
=cpu
, itb
=cpu
.itb
, dtb
=cpu
.dtb
,
178 icache
=getattr(cpu
, 'icache', None),
179 dcache
=getattr(cpu
, 'dcache', None),
180 l2cache
=getattr(self
, 'l2', None))
184 def connectMemSide(self
, bus
):
187 self
.l2
.mem_side
= bus
.slave
188 except AttributeError:
189 for cpu
in self
.cpus
:
190 cpu
.connectAllPorts(bus
)
193 class AtomicCluster(CpuCluster
):
194 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
195 cpu_config
= [ ObjectList
.cpu_list
.get("AtomicSimpleCPU"), None,
197 super(AtomicCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
198 cpu_voltage
, *cpu_config
)
202 class KvmCluster(CpuCluster
):
203 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
204 cpu_config
= [ ObjectList
.cpu_list
.get("ArmV8KvmCPU"), None, None,
206 super(KvmCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
207 cpu_voltage
, *cpu_config
)
211 class FastmodelCluster(SubSystem
):
212 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
213 super(FastmodelCluster
, self
).__init
__()
216 gic
= system
.realview
.gic
217 gic
.sc_gic
.cpu_affinities
= ','.join(
218 [ '0.0.%d.0' % i
for i
in range(num_cpus
) ])
220 # Parse the base address of redistributor.
221 redist_base
= gic
.get_redist_bases()[0]
222 redist_frame_size
= 0x40000 if gic
.sc_gic
.has_gicv4_1
else 0x20000
223 gic
.sc_gic
.reg_base_per_redistributor
= ','.join([
224 '0.0.%d.0=%#x' % (i
, redist_base
+ redist_frame_size
* i
)
225 for i
in range(num_cpus
)
228 gic_a2t
= AmbaToTlmBridge64(amba
=gic
.amba_m
)
229 gic_t2g
= TlmToGem5Bridge64(tlm
=gic_a2t
.tlm
, gem5
=system
.iobus
.slave
)
230 gic_g2t
= Gem5ToTlmBridge64(gem5
=system
.membus
.master
)
231 gic_g2t
.addr_ranges
= gic
.get_addr_ranges()
232 gic_t2a
= AmbaFromTlmBridge64(tlm
=gic_g2t
.tlm
)
233 gic
.amba_s
= gic_t2a
.amba
235 system
.gic_hub
= SubSystem()
236 system
.gic_hub
.gic_a2t
= gic_a2t
237 system
.gic_hub
.gic_t2g
= gic_t2g
238 system
.gic_hub
.gic_g2t
= gic_g2t
239 system
.gic_hub
.gic_t2a
= gic_t2a
241 self
.voltage_domain
= VoltageDomain(voltage
=cpu_voltage
)
242 self
.clk_domain
= SrcClockDomain(clock
=cpu_clock
,
243 voltage_domain
=self
.voltage_domain
)
247 CpuClasses
= [FastModelCortexA76x1
, FastModelCortexA76x2
,
248 FastModelCortexA76x3
, FastModelCortexA76x4
]
249 CpuClass
= CpuClasses
[num_cpus
- 1]
251 cpu
= CpuClass(GICDISABLE
=False)
252 for core
in cpu
.cores
:
253 core
.semihosting_enable
= False
254 core
.RVBARADDR
= 0x10
255 core
.redistributor
= gic
.redistributor
258 a2t
= AmbaToTlmBridge64(amba
=cpu
.amba
)
259 t2g
= TlmToGem5Bridge64(tlm
=a2t
.tlm
, gem5
=system
.membus
.slave
)
260 system
.gic_hub
.a2t
= a2t
261 system
.gic_hub
.t2g
= t2g
263 system
.addCpuCluster(self
, num_cpus
)
265 def requireCaches(self
):
268 def memoryMode(self
):
269 return 'atomic_noncaching'
274 def addL2(self
, clk_domain
):
277 def connectMemSide(self
, bus
):
280 def simpleSystem(BaseSystem
, caches
, mem_size
, platform
=None, **kwargs
):
282 Create a simple system example. The base class in configurable so
283 that it is possible (e.g) to link the platform (hardware configuration)
284 with a baremetal ArmSystem or with a LinuxArmSystem.
286 class SimpleSystem(BaseSystem
):
289 def __init__(self
, caches
, mem_size
, platform
=None, **kwargs
):
290 super(SimpleSystem
, self
).__init
__(**kwargs
)
292 self
.voltage_domain
= VoltageDomain(voltage
="1.0V")
293 self
.clk_domain
= SrcClockDomain(
295 voltage_domain
=Parent
.voltage_domain
)
298 self
.realview
= VExpress_GEM5_V1()
300 self
.realview
= platform
302 if hasattr(self
.realview
.gic
, 'cpu_addr'):
303 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
304 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
306 self
.membus
= MemBus()
308 self
.intrctrl
= IntrControl()
309 self
.terminal
= Terminal()
310 self
.vncserver
= VncServer()
312 self
.iobus
= IOXBar()
314 self
.iobridge
= Bridge(delay
='50ns')
316 mem_range
= self
.realview
._mem
_regions
[0]
317 assert long(mem_range
.size()) >= long(Addr(mem_size
))
319 AddrRange(start
=mem_range
.start
, size
=mem_size
) ]
321 self
._caches
= caches
323 self
.iocache
= IOCache(addr_ranges
=[self
.mem_ranges
[0]])
325 self
.dmabridge
= Bridge(delay
='50ns',
326 ranges
=[self
.mem_ranges
[0]])
331 def attach_pci(self
, dev
):
332 self
.realview
.attachPciDevice(dev
, self
.iobus
)
335 self
.iobridge
.master
= self
.iobus
.slave
336 self
.iobridge
.slave
= self
.membus
.master
339 self
.iocache
.mem_side
= self
.membus
.slave
340 self
.iocache
.cpu_side
= self
.iobus
.master
342 self
.dmabridge
.master
= self
.membus
.slave
343 self
.dmabridge
.slave
= self
.iobus
.master
345 if hasattr(self
.realview
.gic
, 'cpu_addr'):
346 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
347 self
.realview
.attachOnChipIO(self
.membus
, self
.iobridge
)
348 self
.realview
.attachIO(self
.iobus
)
349 self
.system_port
= self
.membus
.slave
351 def numCpuClusters(self
):
352 return len(self
._clusters
)
354 def addCpuCluster(self
, cpu_cluster
, num_cpus
):
355 assert cpu_cluster
not in self
._clusters
357 self
._clusters
.append(cpu_cluster
)
358 self
._num
_cpus
+= num_cpus
361 return self
._num
_cpus
363 def addCaches(self
, need_caches
, last_cache_level
):
365 # connect each cluster to the memory hierarchy
366 for cluster
in self
._clusters
:
367 cluster
.connectMemSide(self
.membus
)
370 cluster_mem_bus
= self
.membus
371 assert last_cache_level
>= 1 and last_cache_level
<= 3
372 for cluster
in self
._clusters
:
374 if last_cache_level
> 1:
375 for cluster
in self
._clusters
:
376 cluster
.addL2(cluster
.clk_domain
)
377 if last_cache_level
> 2:
378 max_clock_cluster
= max(self
._clusters
,
379 key
=lambda c
: c
.clk_domain
.clock
[0])
380 self
.l3
= L3(clk_domain
=max_clock_cluster
.clk_domain
)
381 self
.toL3Bus
= L2XBar(width
=64)
382 self
.toL3Bus
.master
= self
.l3
.cpu_side
383 self
.l3
.mem_side
= self
.membus
.slave
384 cluster_mem_bus
= self
.toL3Bus
386 # connect each cluster to the memory hierarchy
387 for cluster
in self
._clusters
:
388 cluster
.connectMemSide(cluster_mem_bus
)
390 return SimpleSystem(caches
, mem_size
, platform
, **kwargs
)