configs/example/arm/devices.py

   1 # Copyright (c) 2016-2017, 2019 ARM Limited
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   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
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  11 # modified or unmodified, in source code or in binary form.
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  14 # modification, are permitted provided that the following conditions are
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35
  36 # System components used by the bigLITTLE.py configuration script
  37
  38 from __future__ import print_function
  39 from __future__ import absolute_import
  40
  41 import six
  42
  43 import m5
  44 from m5.objects import *
  45 m5.util.addToPath('../../')
  46 from common.Caches import *
  47 from common import ObjectList
  48
  49 if six.PY3:
  50     long = int
  51
  52 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
  53 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()
  54
  55 class L1I(L1_ICache):
  56     tag_latency = 1
  57     data_latency = 1
  58     response_latency = 1
  59     mshrs = 4
  60     tgts_per_mshr = 8
  61     size = '48kB'
  62     assoc = 3
  63
  64
  65 class L1D(L1_DCache):
  66     tag_latency = 2
  67     data_latency = 2
  68     response_latency = 1
  69     mshrs = 16
  70     tgts_per_mshr = 16
  71     size = '32kB'
  72     assoc = 2
  73     write_buffers = 16
  74
  75
  76 class WalkCache(PageTableWalkerCache):
  77     tag_latency = 4
  78     data_latency = 4
  79     response_latency = 4
  80     mshrs = 6
  81     tgts_per_mshr = 8
  82     size = '1kB'
  83     assoc = 8
  84     write_buffers = 16
  85
  86
  87 class L2(L2Cache):
  88     tag_latency = 12
  89     data_latency = 12
  90     response_latency = 5
  91     mshrs = 32
  92     tgts_per_mshr = 8
  93     size = '1MB'
  94     assoc = 16
  95     write_buffers = 8
  96     clusivity='mostly_excl'
  97
  98
  99 class L3(Cache):
 100     size = '16MB'
 101     assoc = 16
 102     tag_latency = 20
 103     data_latency = 20
 104     response_latency = 20
 105     mshrs = 20
 106     tgts_per_mshr = 12
 107     clusivity='mostly_excl'
 108
 109
 110 class MemBus(SystemXBar):
 111     badaddr_responder = BadAddr(warn_access="warn")
 112     default = Self.badaddr_responder.pio
 113
 114
 115 class CpuCluster(SubSystem):
 116     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
 117                  cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
 118         super(CpuCluster, self).__init__()
 119         self._cpu_type = cpu_type
 120         self._l1i_type = l1i_type
 121         self._l1d_type = l1d_type
 122         self._wcache_type = wcache_type
 123         self._l2_type = l2_type
 124
 125         assert num_cpus > 0
 126
 127         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
 128         self.clk_domain = SrcClockDomain(clock=cpu_clock,
 129                                          voltage_domain=self.voltage_domain)
 130
 131         self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
 132                                      clk_domain=self.clk_domain)
 133                       for idx in range(num_cpus) ]
 134
 135         for cpu in self.cpus:
 136             cpu.createThreads()
 137             cpu.createInterruptController()
 138             cpu.socket_id = system.numCpuClusters()
 139         system.addCpuCluster(self, num_cpus)
 140
 141     def requireCaches(self):
 142         return self._cpu_type.require_caches()
 143
 144     def memoryMode(self):
 145         return self._cpu_type.memory_mode()
 146
 147     def addL1(self):
 148         for cpu in self.cpus:
 149             l1i = None if self._l1i_type is None else self._l1i_type()
 150             l1d = None if self._l1d_type is None else self._l1d_type()
 151             iwc = None if self._wcache_type is None else self._wcache_type()
 152             dwc = None if self._wcache_type is None else self._wcache_type()
 153             cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
 154
 155     def addL2(self, clk_domain):
 156         if self._l2_type is None:
 157             return
 158         self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
 159         self.l2 = self._l2_type()
 160         for cpu in self.cpus:
 161             cpu.connectAllPorts(self.toL2Bus)
 162         self.toL2Bus.master = self.l2.cpu_side
 163
 164     def addPMUs(self, ints, events=[]):
 165         """
 166         Instantiates 1 ArmPMU per PE. The method is accepting a list of
 167         interrupt numbers (ints) used by the PMU and a list of events to
 168         register in it.
 169
 170         :param ints: List of interrupt numbers. The code will iterate over
 171             the cpu list in order and will assign to every cpu in the cluster
 172             a PMU with the matching interrupt.
 173         :type ints: List[int]
 174         :param events: Additional events to be measured by the PMUs
 175         :type events: List[Union[ProbeEvent, SoftwareIncrement]]
 176         """
 177         assert len(ints) == len(self.cpus)
 178         for cpu, pint in zip(self.cpus, ints):
 179             int_cls = ArmPPI if pint < 32 else ArmSPI
 180             for isa in cpu.isa:
 181                 isa.pmu = ArmPMU(interrupt=int_cls(num=pint))
 182                 isa.pmu.addArchEvents(cpu=cpu, itb=cpu.itb, dtb=cpu.dtb,
 183                                       icache=getattr(cpu, 'icache', None),
 184                                       dcache=getattr(cpu, 'dcache', None),
 185                                       l2cache=getattr(self, 'l2', None))
 186                 for ev in events:
 187                     isa.pmu.addEvent(ev)
 188
 189     def connectMemSide(self, bus):
 190         bus.slave
 191         try:
 192             self.l2.mem_side = bus.slave
 193         except AttributeError:
 194             for cpu in self.cpus:
 195                 cpu.connectAllPorts(bus)
 196
 197
 198 class AtomicCluster(CpuCluster):
 199     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 200         cpu_config = [ ObjectList.cpu_list.get("AtomicSimpleCPU"), None,
 201                        None, None, None ]
 202         super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 203                                             cpu_voltage, *cpu_config)
 204     def addL1(self):
 205         pass
 206
 207 class KvmCluster(CpuCluster):
 208     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 209         cpu_config = [ ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,
 210             None, None ]
 211         super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
 212                                          cpu_voltage, *cpu_config)
 213     def addL1(self):
 214         pass
 215
 216 class FastmodelCluster(SubSystem):
 217     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage="1.0V"):
 218         super(FastmodelCluster, self).__init__()
 219
 220         # Setup GIC
 221         gic = system.realview.gic
 222         gic.sc_gic.cpu_affinities = ','.join(
 223             [ '0.0.%d.0' % i for i in range(num_cpus) ])
 224
 225         # Parse the base address of redistributor.
 226         redist_base = gic.get_redist_bases()[0]
 227         redist_frame_size = 0x40000 if gic.sc_gic.has_gicv4_1 else 0x20000
 228         gic.sc_gic.reg_base_per_redistributor = ','.join([
 229             '0.0.%d.0=%#x' % (i, redist_base + redist_frame_size * i)
 230             for i in range(num_cpus)
 231         ])
 232
 233         gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m)
 234         gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, gem5=system.iobus.slave)
 235         gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master)
 236         gic_g2t.addr_ranges = gic.get_addr_ranges()
 237         gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm)
 238         gic.amba_s = gic_t2a.amba
 239
 240         system.gic_hub = SubSystem()
 241         system.gic_hub.gic_a2t = gic_a2t
 242         system.gic_hub.gic_t2g = gic_t2g
 243         system.gic_hub.gic_g2t = gic_g2t
 244         system.gic_hub.gic_t2a = gic_t2a
 245
 246         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
 247         self.clk_domain = SrcClockDomain(clock=cpu_clock,
 248                                          voltage_domain=self.voltage_domain)
 249
 250         # Setup CPU
 251         assert num_cpus <= 4
 252         CpuClasses = [FastModelCortexA76x1, FastModelCortexA76x2,
 253                       FastModelCortexA76x3, FastModelCortexA76x4]
 254         CpuClass = CpuClasses[num_cpus - 1]
 255
 256         cpu = CpuClass(GICDISABLE=False)
 257         for core in cpu.cores:
 258             core.semihosting_enable = False
 259             core.RVBARADDR = 0x10
 260             core.redistributor = gic.redistributor
 261         self.cpus = [ cpu ]
 262
 263         a2t = AmbaToTlmBridge64(amba=cpu.amba)
 264         t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave)
 265         system.gic_hub.a2t = a2t
 266         system.gic_hub.t2g = t2g
 267
 268         system.addCpuCluster(self, num_cpus)
 269
 270     def requireCaches(self):
 271         return False
 272
 273     def memoryMode(self):
 274         return 'atomic_noncaching'
 275
 276     def addL1(self):
 277         pass
 278
 279     def addL2(self, clk_domain):
 280         pass
 281
 282     def connectMemSide(self, bus):
 283         pass
 284
 285 def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs):
 286     """
 287     Create a simple system example.  The base class in configurable so
 288     that it is possible (e.g) to link the platform (hardware configuration)
 289     with a baremetal ArmSystem or with a LinuxArmSystem.
 290     """
 291     class SimpleSystem(BaseSystem):
 292         cache_line_size = 64
 293
 294         def __init__(self, caches, mem_size, platform=None, **kwargs):
 295             super(SimpleSystem, self).__init__(**kwargs)
 296
 297             self.voltage_domain = VoltageDomain(voltage="1.0V")
 298             self.clk_domain = SrcClockDomain(
 299                 clock="1GHz",
 300                 voltage_domain=Parent.voltage_domain)
 301
 302             if platform is None:
 303                 self.realview = VExpress_GEM5_V1()
 304             else:
 305                 self.realview = platform
 306
 307             if hasattr(self.realview.gic, 'cpu_addr'):
 308                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 309             self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 310
 311             self.membus = MemBus()
 312
 313             self.intrctrl = IntrControl()
 314             self.terminal = Terminal()
 315             self.vncserver = VncServer()
 316
 317             self.iobus = IOXBar()
 318             # CPUs->PIO
 319             self.iobridge = Bridge(delay='50ns')
 320             # Device DMA -> MEM
 321             mem_range = self.realview._mem_regions[0]
 322             assert long(mem_range.size()) >= long(Addr(mem_size))
 323             self.mem_ranges = [
 324                 AddrRange(start=mem_range.start, size=mem_size) ]
 325
 326             self._caches = caches
 327             if self._caches:
 328                 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
 329             else:
 330                 self.dmabridge = Bridge(delay='50ns',
 331                                         ranges=[self.mem_ranges[0]])
 332
 333             self._clusters = []
 334             self._num_cpus = 0
 335
 336         def attach_pci(self, dev):
 337             self.realview.attachPciDevice(dev, self.iobus)
 338
 339         def connect(self):
 340             self.iobridge.master = self.iobus.slave
 341             self.iobridge.slave = self.membus.master
 342
 343             if self._caches:
 344                 self.iocache.mem_side = self.membus.slave
 345                 self.iocache.cpu_side = self.iobus.master
 346             else:
 347                 self.dmabridge.master = self.membus.slave
 348                 self.dmabridge.slave = self.iobus.master
 349
 350             if hasattr(self.realview.gic, 'cpu_addr'):
 351                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 352             self.realview.attachOnChipIO(self.membus, self.iobridge)
 353             self.realview.attachIO(self.iobus)
 354             self.system_port = self.membus.slave
 355
 356         def numCpuClusters(self):
 357             return len(self._clusters)
 358
 359         def addCpuCluster(self, cpu_cluster, num_cpus):
 360             assert cpu_cluster not in self._clusters
 361             assert num_cpus > 0
 362             self._clusters.append(cpu_cluster)
 363             self._num_cpus += num_cpus
 364
 365         def numCpus(self):
 366             return self._num_cpus
 367
 368         def addCaches(self, need_caches, last_cache_level):
 369             if not need_caches:
 370                 # connect each cluster to the memory hierarchy
 371                 for cluster in self._clusters:
 372                     cluster.connectMemSide(self.membus)
 373                 return
 374
 375             cluster_mem_bus = self.membus
 376             assert last_cache_level >= 1 and last_cache_level <= 3
 377             for cluster in self._clusters:
 378                 cluster.addL1()
 379             if last_cache_level > 1:
 380                 for cluster in self._clusters:
 381                     cluster.addL2(cluster.clk_domain)
 382             if last_cache_level > 2:
 383                 max_clock_cluster = max(self._clusters,
 384                                         key=lambda c: c.clk_domain.clock[0])
 385                 self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
 386                 self.toL3Bus = L2XBar(width=64)
 387                 self.toL3Bus.master = self.l3.cpu_side
 388                 self.l3.mem_side = self.membus.slave
 389                 cluster_mem_bus = self.toL3Bus
 390
 391             # connect each cluster to the memory hierarchy
 392             for cluster in self._clusters:
 393                 cluster.connectMemSide(cluster_mem_bus)
 394
 395     return SimpleSystem(caches, mem_size, platform, **kwargs)