1 # Copyright (c) 2016 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
39 # System components used by the bigLITTLE.py configuration script
42 from m5
.objects
import *
43 m5
.util
.addToPath('../../')
44 from common
.Caches
import *
45 from common
import CpuConfig
68 class WalkCache(PageTableWalkerCache
):
88 clusivity
='mostly_excl'
99 clusivity
='mostly_excl'
102 class MemBus(SystemXBar
):
103 badaddr_responder
= BadAddr(warn_access
="warn")
104 default
= Self
.badaddr_responder
.pio
107 class CpuCluster(SubSystem
):
108 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
,
109 cpu_type
, l1i_type
, l1d_type
, wcache_type
, l2_type
):
110 super(CpuCluster
, self
).__init
__()
111 self
._cpu
_type
= cpu_type
112 self
._l1i
_type
= l1i_type
113 self
._l1d
_type
= l1d_type
114 self
._wcache
_type
= wcache_type
115 self
._l2_type
= l2_type
119 self
.voltage_domain
= VoltageDomain(voltage
=cpu_voltage
)
120 self
.clk_domain
= SrcClockDomain(clock
=cpu_clock
,
121 voltage_domain
=self
.voltage_domain
)
123 self
.cpus
= [ self
._cpu
_type
(cpu_id
=system
.numCpus() + idx
,
124 clk_domain
=self
.clk_domain
)
125 for idx
in range(num_cpus
) ]
127 for cpu
in self
.cpus
:
129 cpu
.createInterruptController()
130 cpu
.socket_id
= system
.numCpuClusters()
131 system
.addCpuCluster(self
, num_cpus
)
133 def requireCaches(self
):
134 return self
._cpu
_type
.require_caches()
136 def memoryMode(self
):
137 return self
._cpu
_type
.memory_mode()
140 for cpu
in self
.cpus
:
141 l1i
= None if self
._l1i
_type
is None else self
._l1i
_type
()
142 l1d
= None if self
._l1d
_type
is None else self
._l1d
_type
()
143 iwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
144 dwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
145 cpu
.addPrivateSplitL1Caches(l1i
, l1d
, iwc
, dwc
)
147 def addL2(self
, clk_domain
):
148 if self
._l2_type
is None:
150 self
.toL2Bus
= L2XBar(width
=64, clk_domain
=clk_domain
)
151 self
.l2
= self
._l2_type
()
152 for cpu
in self
.cpus
:
153 cpu
.connectAllPorts(self
.toL2Bus
)
154 self
.toL2Bus
.master
= self
.l2
.cpu_side
156 def connectMemSide(self
, bus
):
159 self
.l2
.mem_side
= bus
.slave
160 except AttributeError:
161 for cpu
in self
.cpus
:
162 cpu
.connectAllPorts(bus
)
165 class AtomicCluster(CpuCluster
):
166 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
167 cpu_config
= [ CpuConfig
.get("atomic"), None, None, None, None ]
168 super(AtomicCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
169 cpu_voltage
, *cpu_config
)
174 class SimpleSystem(LinuxArmSystem
):
177 def __init__(self
, caches
, mem_size
, **kwargs
):
178 super(SimpleSystem
, self
).__init
__(**kwargs
)
180 self
.voltage_domain
= VoltageDomain(voltage
="1.0V")
181 self
.clk_domain
= SrcClockDomain(clock
="1GHz",
182 voltage_domain
=Parent
.voltage_domain
)
184 self
.realview
= VExpress_GEM5_V1()
186 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
187 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
189 self
.membus
= MemBus()
191 self
.intrctrl
= IntrControl()
192 self
.terminal
= Terminal()
193 self
.vncserver
= VncServer()
195 self
.iobus
= IOXBar()
197 self
.iobridge
= Bridge(delay
='50ns')
199 mem_range
= self
.realview
._mem
_regions
[0]
200 mem_range_size
= long(mem_range
[1]) - long(mem_range
[0])
201 assert mem_range_size
>= long(Addr(mem_size
))
202 self
._mem
_range
= AddrRange(start
=mem_range
[0], size
=mem_size
)
203 self
._caches
= caches
205 self
.iocache
= IOCache(addr_ranges
=[self
._mem
_range
])
207 self
.dmabridge
= Bridge(delay
='50ns',
208 ranges
=[self
._mem
_range
])
210 self
._pci
_devices
= 0
214 def attach_pci(self
, dev
):
215 dev
.pci_bus
, dev
.pci_dev
, dev
.pci_func
= (0, self
._pci
_devices
+ 1, 0)
216 self
._pci
_devices
+= 1
217 self
.realview
.attachPciDevice(dev
, self
.iobus
)
220 self
.iobridge
.master
= self
.iobus
.slave
221 self
.iobridge
.slave
= self
.membus
.master
224 self
.iocache
.mem_side
= self
.membus
.slave
225 self
.iocache
.cpu_side
= self
.iobus
.master
227 self
.dmabridge
.master
= self
.membus
.slave
228 self
.dmabridge
.slave
= self
.iobus
.master
230 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
231 self
.realview
.attachOnChipIO(self
.membus
, self
.iobridge
)
232 self
.realview
.attachIO(self
.iobus
)
233 self
.system_port
= self
.membus
.slave
235 def numCpuClusters(self
):
236 return len(self
._clusters
)
238 def addCpuCluster(self
, cpu_cluster
, num_cpus
):
239 assert cpu_cluster
not in self
._clusters
241 self
._clusters
.append(cpu_cluster
)
242 self
._num
_cpus
+= num_cpus
245 return self
._num
_cpus
247 def addCaches(self
, need_caches
, last_cache_level
):
249 # connect each cluster to the memory hierarchy
250 for cluster
in self
._clusters
:
251 cluster
.connectMemSide(self
.membus
)
254 cluster_mem_bus
= self
.membus
255 assert last_cache_level
>= 1 and last_cache_level
<= 3
256 for cluster
in self
._clusters
:
258 if last_cache_level
> 1:
259 for cluster
in self
._clusters
:
260 cluster
.addL2(cluster
.clk_domain
)
261 if last_cache_level
> 2:
262 max_clock_cluster
= max(self
._clusters
,
263 key
=lambda c
: c
.clk_domain
.clock
[0])
264 self
.l3
= L3(clk_domain
=max_clock_cluster
.clk_domain
)
265 self
.toL3Bus
= L2XBar(width
=64)
266 self
.toL3Bus
.master
= self
.l3
.cpu_side
267 self
.l3
.mem_side
= self
.membus
.slave
268 cluster_mem_bus
= self
.toL3Bus
270 # connect each cluster to the memory hierarchy
271 for cluster
in self
._clusters
:
272 cluster
.connectMemSide(cluster_mem_bus
)