configs/example/arm/devices.py

   1 # Copyright (c) 2016-2017, 2019 ARM Limited
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   3 #
   4 # The license below extends only to copyright in the software and shall
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  11 # modified or unmodified, in source code or in binary form.
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  14 # modification, are permitted provided that the following conditions are
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35
  36 # System components used by the bigLITTLE.py configuration script
  37
  38 from __future__ import print_function
  39 from __future__ import absolute_import
  40
  41 import m5
  42 from m5.objects import *
  43 m5.util.addToPath('../../')
  44 from common.Caches import *
  45 from common import ObjectList
  46
  47 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
  48 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()
  49
  50 class L1I(L1_ICache):
  51     tag_latency = 1
  52     data_latency = 1
  53     response_latency = 1
  54     mshrs = 4
  55     tgts_per_mshr = 8
  56     size = '48kB'
  57     assoc = 3
  58
  59
  60 class L1D(L1_DCache):
  61     tag_latency = 2
  62     data_latency = 2
  63     response_latency = 1
  64     mshrs = 16
  65     tgts_per_mshr = 16
  66     size = '32kB'
  67     assoc = 2
  68     write_buffers = 16
  69
  70
  71 class WalkCache(PageTableWalkerCache):
  72     tag_latency = 4
  73     data_latency = 4
  74     response_latency = 4
  75     mshrs = 6
  76     tgts_per_mshr = 8
  77     size = '1kB'
  78     assoc = 8
  79     write_buffers = 16
  80
  81
  82 class L2(L2Cache):
  83     tag_latency = 12
  84     data_latency = 12
  85     response_latency = 5
  86     mshrs = 32
  87     tgts_per_mshr = 8
  88     size = '1MB'
  89     assoc = 16
  90     write_buffers = 8
  91     clusivity='mostly_excl'
  92
  93
  94 class L3(Cache):
  95     size = '16MB'
  96     assoc = 16
  97     tag_latency = 20
  98     data_latency = 20
  99     response_latency = 20
 100     mshrs = 20
 101     tgts_per_mshr = 12
 102     clusivity='mostly_excl'
 103
 104
 105 class MemBus(SystemXBar):
 106     badaddr_responder = BadAddr(warn_access="warn")
 107     default = Self.badaddr_responder.pio
 108
 109
 110 class CpuCluster(SubSystem):
 111     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
 112                  cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
 113         super(CpuCluster, self).__init__()
 114         self._cpu_type = cpu_type
 115         self._l1i_type = l1i_type
 116         self._l1d_type = l1d_type
 117         self._wcache_type = wcache_type
 118         self._l2_type = l2_type
 119
 120         assert num_cpus > 0
 121
 122         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
 123         self.clk_domain = SrcClockDomain(clock=cpu_clock,
 124                                          voltage_domain=self.voltage_domain)
 125
 126         self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
 127                                      clk_domain=self.clk_domain)
 128                       for idx in range(num_cpus) ]
 129
 130         for cpu in self.cpus:
 131             cpu.createThreads()
 132             cpu.createInterruptController()
 133             cpu.socket_id = system.numCpuClusters()
 134         system.addCpuCluster(self, num_cpus)
 135
 136     def requireCaches(self):
 137         return self._cpu_type.require_caches()
 138
 139     def memoryMode(self):
 140         return self._cpu_type.memory_mode()
 141
 142     def addL1(self):
 143         for cpu in self.cpus:
 144             l1i = None if self._l1i_type is None else self._l1i_type()
 145             l1d = None if self._l1d_type is None else self._l1d_type()
 146             iwc = None if self._wcache_type is None else self._wcache_type()
 147             dwc = None if self._wcache_type is None else self._wcache_type()
 148             cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
 149
 150     def addL2(self, clk_domain):
 151         if self._l2_type is None:
 152             return
 153         self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
 154         self.l2 = self._l2_type()
 155         for cpu in self.cpus:
 156             cpu.connectAllPorts(self.toL2Bus)
 157         self.toL2Bus.master = self.l2.cpu_side
 158
 159     def addPMUs(self, ints, events=[]):
 160         """
 161         Instantiates 1 ArmPMU per PE. The method is accepting a list of
 162         interrupt numbers (ints) used by the PMU and a list of events to
 163         register in it.
 164
 165         :param ints: List of interrupt numbers. The code will iterate over
 166             the cpu list in order and will assign to every cpu in the cluster
 167             a PMU with the matching interrupt.
 168         :type ints: List[int]
 169         :param events: Additional events to be measured by the PMUs
 170         :type events: List[Union[ProbeEvent, SoftwareIncrement]]
 171         """
 172         assert len(ints) == len(self.cpus)
 173         for cpu, pint in zip(self.cpus, ints):
 174             int_cls = ArmPPI if pint < 32 else ArmSPI
 175             for isa in cpu.isa:
 176                 isa.pmu = ArmPMU(interrupt=int_cls(num=pint))
 177                 isa.pmu.addArchEvents(cpu=cpu, itb=cpu.itb, dtb=cpu.dtb,
 178                                       icache=getattr(cpu, 'icache', None),
 179                                       dcache=getattr(cpu, 'dcache', None),
 180                                       l2cache=getattr(self, 'l2', None))
 181                 for ev in events:
 182                     isa.pmu.addEvent(ev)
 183
 184     def connectMemSide(self, bus):
 185         bus.slave
 186         try:
 187             self.l2.mem_side = bus.slave
 188         except AttributeError:
 189             for cpu in self.cpus:
 190                 cpu.connectAllPorts(bus)
 191
 192
 193 class AtomicCluster(CpuCluster):
 194     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 195         cpu_config = [ ObjectList.cpu_list.get("AtomicSimpleCPU"), None,
 196                        None, None, None ]
 197         super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 198                                             cpu_voltage, *cpu_config)
 199     def addL1(self):
 200         pass
 201
 202 class KvmCluster(CpuCluster):
 203     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 204         cpu_config = [ ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,
 205             None, None ]
 206         super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
 207                                          cpu_voltage, *cpu_config)
 208     def addL1(self):
 209         pass
 210
 211 class FastmodelCluster(SubSystem):
 212     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage="1.0V"):
 213         super(FastmodelCluster, self).__init__()
 214
 215         # Setup GIC
 216         gic = system.realview.gic
 217         gic.sc_gic.cpu_affinities = ','.join(
 218             [ '0.0.%d.0' % i for i in range(num_cpus) ])
 219
 220         # Parse the base address of redistributor.
 221         redist_base = gic.get_redist_bases()[0]
 222         redist_frame_size = 0x40000 if gic.sc_gic.has_gicv4_1 else 0x20000
 223         gic.sc_gic.reg_base_per_redistributor = ','.join([
 224             '0.0.%d.0=%#x' % (i, redist_base + redist_frame_size * i)
 225             for i in range(num_cpus)
 226         ])
 227
 228         gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m)
 229         gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, gem5=system.iobus.slave)
 230         gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master)
 231         gic_g2t.addr_ranges = gic.get_addr_ranges()
 232         gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm)
 233         gic.amba_s = gic_t2a.amba
 234
 235         system.gic_hub = SubSystem()
 236         system.gic_hub.gic_a2t = gic_a2t
 237         system.gic_hub.gic_t2g = gic_t2g
 238         system.gic_hub.gic_g2t = gic_g2t
 239         system.gic_hub.gic_t2a = gic_t2a
 240
 241         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
 242         self.clk_domain = SrcClockDomain(clock=cpu_clock,
 243                                          voltage_domain=self.voltage_domain)
 244
 245         # Setup CPU
 246         assert num_cpus <= 4
 247         CpuClasses = [FastModelCortexA76x1, FastModelCortexA76x2,
 248                       FastModelCortexA76x3, FastModelCortexA76x4]
 249         CpuClass = CpuClasses[num_cpus - 1]
 250
 251         cpu = CpuClass(GICDISABLE=False)
 252         for core in cpu.cores:
 253             core.semihosting_enable = False
 254             core.RVBARADDR = 0x10
 255             core.redistributor = gic.redistributor
 256         self.cpus = [ cpu ]
 257
 258         a2t = AmbaToTlmBridge64(amba=cpu.amba)
 259         t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave)
 260         system.gic_hub.a2t = a2t
 261         system.gic_hub.t2g = t2g
 262
 263         system.addCpuCluster(self, num_cpus)
 264
 265     def requireCaches(self):
 266         return False
 267
 268     def memoryMode(self):
 269         return 'atomic_noncaching'
 270
 271     def addL1(self):
 272         pass
 273
 274     def addL2(self, clk_domain):
 275         pass
 276
 277     def connectMemSide(self, bus):
 278         pass
 279
 280 def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs):
 281     """
 282     Create a simple system example.  The base class in configurable so
 283     that it is possible (e.g) to link the platform (hardware configuration)
 284     with a baremetal ArmSystem or with a LinuxArmSystem.
 285     """
 286     class SimpleSystem(BaseSystem):
 287         cache_line_size = 64
 288
 289         def __init__(self, caches, mem_size, platform=None, **kwargs):
 290             super(SimpleSystem, self).__init__(**kwargs)
 291
 292             self.voltage_domain = VoltageDomain(voltage="1.0V")
 293             self.clk_domain = SrcClockDomain(
 294                 clock="1GHz",
 295                 voltage_domain=Parent.voltage_domain)
 296
 297             if platform is None:
 298                 self.realview = VExpress_GEM5_V1()
 299             else:
 300                 self.realview = platform
 301
 302             if hasattr(self.realview.gic, 'cpu_addr'):
 303                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 304             self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 305
 306             self.membus = MemBus()
 307
 308             self.intrctrl = IntrControl()
 309             self.terminal = Terminal()
 310             self.vncserver = VncServer()
 311
 312             self.iobus = IOXBar()
 313             # CPUs->PIO
 314             self.iobridge = Bridge(delay='50ns')
 315             # Device DMA -> MEM
 316             mem_range = self.realview._mem_regions[0]
 317             assert long(mem_range.size()) >= long(Addr(mem_size))
 318             self.mem_ranges = [
 319                 AddrRange(start=mem_range.start, size=mem_size) ]
 320
 321             self._caches = caches
 322             if self._caches:
 323                 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
 324             else:
 325                 self.dmabridge = Bridge(delay='50ns',
 326                                         ranges=[self.mem_ranges[0]])
 327
 328             self._clusters = []
 329             self._num_cpus = 0
 330
 331         def attach_pci(self, dev):
 332             self.realview.attachPciDevice(dev, self.iobus)
 333
 334         def connect(self):
 335             self.iobridge.master = self.iobus.slave
 336             self.iobridge.slave = self.membus.master
 337
 338             if self._caches:
 339                 self.iocache.mem_side = self.membus.slave
 340                 self.iocache.cpu_side = self.iobus.master
 341             else:
 342                 self.dmabridge.master = self.membus.slave
 343                 self.dmabridge.slave = self.iobus.master
 344
 345             if hasattr(self.realview.gic, 'cpu_addr'):
 346                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 347             self.realview.attachOnChipIO(self.membus, self.iobridge)
 348             self.realview.attachIO(self.iobus)
 349             self.system_port = self.membus.slave
 350
 351         def numCpuClusters(self):
 352             return len(self._clusters)
 353
 354         def addCpuCluster(self, cpu_cluster, num_cpus):
 355             assert cpu_cluster not in self._clusters
 356             assert num_cpus > 0
 357             self._clusters.append(cpu_cluster)
 358             self._num_cpus += num_cpus
 359
 360         def numCpus(self):
 361             return self._num_cpus
 362
 363         def addCaches(self, need_caches, last_cache_level):
 364             if not need_caches:
 365                 # connect each cluster to the memory hierarchy
 366                 for cluster in self._clusters:
 367                     cluster.connectMemSide(self.membus)
 368                 return
 369
 370             cluster_mem_bus = self.membus
 371             assert last_cache_level >= 1 and last_cache_level <= 3
 372             for cluster in self._clusters:
 373                 cluster.addL1()
 374             if last_cache_level > 1:
 375                 for cluster in self._clusters:
 376                     cluster.addL2(cluster.clk_domain)
 377             if last_cache_level > 2:
 378                 max_clock_cluster = max(self._clusters,
 379                                         key=lambda c: c.clk_domain.clock[0])
 380                 self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
 381                 self.toL3Bus = L2XBar(width=64)
 382                 self.toL3Bus.master = self.l3.cpu_side
 383                 self.l3.mem_side = self.membus.slave
 384                 cluster_mem_bus = self.toL3Bus
 385
 386             # connect each cluster to the memory hierarchy
 387             for cluster in self._clusters:
 388                 cluster.connectMemSide(cluster_mem_bus)
 389
 390     return SimpleSystem(caches, mem_size, platform, **kwargs)