configs/example/arm/devices.py

   1 # Copyright (c) 2016-2017, 2019 ARM Limited
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   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
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  14 # modification, are permitted provided that the following conditions are
  15 # met: redistributions of source code must retain the above copyright
  16 # notice, this list of conditions and the following disclaimer;
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  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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  30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Andreas Sandberg
  37 #          Gabor Dozsa
  38
  39 # System components used by the bigLITTLE.py configuration script
  40
  41 from __future__ import print_function
  42 from __future__ import absolute_import
  43
  44 import m5
  45 from m5.objects import *
  46 m5.util.addToPath('../../')
  47 from common.Caches import *
  48 from common import ObjectList
  49
  50 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
  51 have_fastmodel = "FastModelCortexA76" in ObjectList.cpu_list.get_names()
  52
  53 class L1I(L1_ICache):
  54     tag_latency = 1
  55     data_latency = 1
  56     response_latency = 1
  57     mshrs = 4
  58     tgts_per_mshr = 8
  59     size = '48kB'
  60     assoc = 3
  61
  62
  63 class L1D(L1_DCache):
  64     tag_latency = 2
  65     data_latency = 2
  66     response_latency = 1
  67     mshrs = 16
  68     tgts_per_mshr = 16
  69     size = '32kB'
  70     assoc = 2
  71     write_buffers = 16
  72
  73
  74 class WalkCache(PageTableWalkerCache):
  75     tag_latency = 4
  76     data_latency = 4
  77     response_latency = 4
  78     mshrs = 6
  79     tgts_per_mshr = 8
  80     size = '1kB'
  81     assoc = 8
  82     write_buffers = 16
  83
  84
  85 class L2(L2Cache):
  86     tag_latency = 12
  87     data_latency = 12
  88     response_latency = 5
  89     mshrs = 32
  90     tgts_per_mshr = 8
  91     size = '1MB'
  92     assoc = 16
  93     write_buffers = 8
  94     clusivity='mostly_excl'
  95
  96
  97 class L3(Cache):
  98     size = '16MB'
  99     assoc = 16
 100     tag_latency = 20
 101     data_latency = 20
 102     response_latency = 20
 103     mshrs = 20
 104     tgts_per_mshr = 12
 105     clusivity='mostly_excl'
 106
 107
 108 class MemBus(SystemXBar):
 109     badaddr_responder = BadAddr(warn_access="warn")
 110     default = Self.badaddr_responder.pio
 111
 112
 113 class CpuCluster(SubSystem):
 114     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
 115                  cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
 116         super(CpuCluster, self).__init__()
 117         self._cpu_type = cpu_type
 118         self._l1i_type = l1i_type
 119         self._l1d_type = l1d_type
 120         self._wcache_type = wcache_type
 121         self._l2_type = l2_type
 122
 123         assert num_cpus > 0
 124
 125         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
 126         self.clk_domain = SrcClockDomain(clock=cpu_clock,
 127                                          voltage_domain=self.voltage_domain)
 128
 129         self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
 130                                      clk_domain=self.clk_domain)
 131                       for idx in range(num_cpus) ]
 132
 133         for cpu in self.cpus:
 134             cpu.createThreads()
 135             cpu.createInterruptController()
 136             cpu.socket_id = system.numCpuClusters()
 137         system.addCpuCluster(self, num_cpus)
 138
 139     def requireCaches(self):
 140         return self._cpu_type.require_caches()
 141
 142     def memoryMode(self):
 143         return self._cpu_type.memory_mode()
 144
 145     def addL1(self):
 146         for cpu in self.cpus:
 147             l1i = None if self._l1i_type is None else self._l1i_type()
 148             l1d = None if self._l1d_type is None else self._l1d_type()
 149             iwc = None if self._wcache_type is None else self._wcache_type()
 150             dwc = None if self._wcache_type is None else self._wcache_type()
 151             cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
 152
 153     def addL2(self, clk_domain):
 154         if self._l2_type is None:
 155             return
 156         self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
 157         self.l2 = self._l2_type()
 158         for cpu in self.cpus:
 159             cpu.connectAllPorts(self.toL2Bus)
 160         self.toL2Bus.master = self.l2.cpu_side
 161
 162     def connectMemSide(self, bus):
 163         bus.slave
 164         try:
 165             self.l2.mem_side = bus.slave
 166         except AttributeError:
 167             for cpu in self.cpus:
 168                 cpu.connectAllPorts(bus)
 169
 170
 171 class AtomicCluster(CpuCluster):
 172     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 173         cpu_config = [ ObjectList.cpu_list.get("AtomicSimpleCPU"), None,
 174                        None, None, None ]
 175         super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 176                                             cpu_voltage, *cpu_config)
 177     def addL1(self):
 178         pass
 179
 180 class KvmCluster(CpuCluster):
 181     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 182         cpu_config = [ ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,
 183             None, None ]
 184         super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
 185                                          cpu_voltage, *cpu_config)
 186     def addL1(self):
 187         pass
 188
 189 class FastmodelCluster(SubSystem):
 190     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage="1.0V"):
 191         super(FastmodelCluster, self).__init__()
 192
 193         # Setup GIC
 194         gic = system.realview.gic
 195         gic.sc_gic.cpu_affinities = ','.join(
 196             [ '0.0.%d.0' % i for i in range(num_cpus) ])
 197
 198         # Parse the base address of redistributor.
 199         redist_base = gic.get_redist_bases()[0]
 200         redist_frame_size = 0x40000 if gic.sc_gic.has_gicv4_1 else 0x20000
 201         gic.sc_gic.reg_base_per_redistributor = ','.join([
 202             '0.0.%d.0=%#x' % (i, redist_base + redist_frame_size * i)
 203             for i in range(num_cpus)
 204         ])
 205
 206         gic_a2t = AmbaToTlmBridge64(amba=gic.amba_m)
 207         gic_t2g = TlmToGem5Bridge64(tlm=gic_a2t.tlm, gem5=system.iobus.slave)
 208         gic_g2t = Gem5ToTlmBridge64(gem5=system.membus.master)
 209         gic_g2t.addr_ranges = gic.get_addr_ranges()
 210         gic_t2a = AmbaFromTlmBridge64(tlm=gic_g2t.tlm)
 211         gic.amba_s = gic_t2a.amba
 212
 213         system.gic_hub = SubSystem()
 214         system.gic_hub.gic_a2t = gic_a2t
 215         system.gic_hub.gic_t2g = gic_t2g
 216         system.gic_hub.gic_g2t = gic_g2t
 217         system.gic_hub.gic_t2a = gic_t2a
 218
 219         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
 220         self.clk_domain = SrcClockDomain(clock=cpu_clock,
 221                                          voltage_domain=self.voltage_domain)
 222
 223         # Setup CPU
 224         assert num_cpus <= 4
 225         CpuClasses = [FastModelCortexA76x1, FastModelCortexA76x2,
 226                       FastModelCortexA76x3, FastModelCortexA76x4]
 227         CpuClass = CpuClasses[num_cpus - 1]
 228
 229         cpu = CpuClass(GICDISABLE=False)
 230         for core in cpu.cores:
 231             core.semihosting_enable = False
 232             core.RVBARADDR = 0x10
 233             core.redistributor = gic.redistributor
 234         self.cpus = [ cpu ]
 235
 236         a2t = AmbaToTlmBridge64(amba=cpu.amba)
 237         t2g = TlmToGem5Bridge64(tlm=a2t.tlm, gem5=system.membus.slave)
 238         system.gic_hub.a2t = a2t
 239         system.gic_hub.t2g = t2g
 240
 241         system.addCpuCluster(self, num_cpus)
 242
 243     def requireCaches(self):
 244         return False
 245
 246     def memoryMode(self):
 247         return 'atomic_noncaching'
 248
 249     def addL1(self):
 250         pass
 251
 252     def addL2(self, clk_domain):
 253         pass
 254
 255     def connectMemSide(self, bus):
 256         pass
 257
 258 def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs):
 259     """
 260     Create a simple system example.  The base class in configurable so
 261     that it is possible (e.g) to link the platform (hardware configuration)
 262     with a baremetal ArmSystem or with a LinuxArmSystem.
 263     """
 264     class SimpleSystem(BaseSystem):
 265         cache_line_size = 64
 266
 267         def __init__(self, caches, mem_size, platform=None, **kwargs):
 268             super(SimpleSystem, self).__init__(**kwargs)
 269
 270             self.voltage_domain = VoltageDomain(voltage="1.0V")
 271             self.clk_domain = SrcClockDomain(
 272                 clock="1GHz",
 273                 voltage_domain=Parent.voltage_domain)
 274
 275             if platform is None:
 276                 self.realview = VExpress_GEM5_V1()
 277             else:
 278                 self.realview = platform
 279
 280             if hasattr(self.realview.gic, 'cpu_addr'):
 281                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 282             self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 283
 284             self.membus = MemBus()
 285
 286             self.intrctrl = IntrControl()
 287             self.terminal = Terminal()
 288             self.vncserver = VncServer()
 289
 290             self.iobus = IOXBar()
 291             # CPUs->PIO
 292             self.iobridge = Bridge(delay='50ns')
 293             # Device DMA -> MEM
 294             mem_range = self.realview._mem_regions[0]
 295             assert long(mem_range.size()) >= long(Addr(mem_size))
 296             self.mem_ranges = [
 297                 AddrRange(start=mem_range.start, size=mem_size) ]
 298
 299             self._caches = caches
 300             if self._caches:
 301                 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
 302             else:
 303                 self.dmabridge = Bridge(delay='50ns',
 304                                         ranges=[self.mem_ranges[0]])
 305
 306             self._clusters = []
 307             self._num_cpus = 0
 308
 309         def attach_pci(self, dev):
 310             self.realview.attachPciDevice(dev, self.iobus)
 311
 312         def connect(self):
 313             self.iobridge.master = self.iobus.slave
 314             self.iobridge.slave = self.membus.master
 315
 316             if self._caches:
 317                 self.iocache.mem_side = self.membus.slave
 318                 self.iocache.cpu_side = self.iobus.master
 319             else:
 320                 self.dmabridge.master = self.membus.slave
 321                 self.dmabridge.slave = self.iobus.master
 322
 323             if hasattr(self.realview.gic, 'cpu_addr'):
 324                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 325             self.realview.attachOnChipIO(self.membus, self.iobridge)
 326             self.realview.attachIO(self.iobus)
 327             self.system_port = self.membus.slave
 328
 329         def numCpuClusters(self):
 330             return len(self._clusters)
 331
 332         def addCpuCluster(self, cpu_cluster, num_cpus):
 333             assert cpu_cluster not in self._clusters
 334             assert num_cpus > 0
 335             self._clusters.append(cpu_cluster)
 336             self._num_cpus += num_cpus
 337
 338         def numCpus(self):
 339             return self._num_cpus
 340
 341         def addCaches(self, need_caches, last_cache_level):
 342             if not need_caches:
 343                 # connect each cluster to the memory hierarchy
 344                 for cluster in self._clusters:
 345                     cluster.connectMemSide(self.membus)
 346                 return
 347
 348             cluster_mem_bus = self.membus
 349             assert last_cache_level >= 1 and last_cache_level <= 3
 350             for cluster in self._clusters:
 351                 cluster.addL1()
 352             if last_cache_level > 1:
 353                 for cluster in self._clusters:
 354                     cluster.addL2(cluster.clk_domain)
 355             if last_cache_level > 2:
 356                 max_clock_cluster = max(self._clusters,
 357                                         key=lambda c: c.clk_domain.clock[0])
 358                 self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
 359                 self.toL3Bus = L2XBar(width=64)
 360                 self.toL3Bus.master = self.l3.cpu_side
 361                 self.l3.mem_side = self.membus.slave
 362                 cluster_mem_bus = self.toL3Bus
 363
 364             # connect each cluster to the memory hierarchy
 365             for cluster in self._clusters:
 366                 cluster.connectMemSide(cluster_mem_bus)
 367
 368     return SimpleSystem(caches, mem_size, platform, **kwargs)