configs/example/arm/devices.py

   1 # Copyright (c) 2016-2017, 2019 ARM Limited
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  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 # Authors: Andreas Sandberg
  37 #          Gabor Dozsa
  38
  39 # System components used by the bigLITTLE.py configuration script
  40
  41 from __future__ import print_function
  42 from __future__ import absolute_import
  43
  44 import m5
  45 from m5.objects import *
  46 m5.util.addToPath('../../')
  47 from common.Caches import *
  48 from common import ObjectList
  49
  50 have_kvm = "ArmV8KvmCPU" in ObjectList.cpu_list.get_names()
  51
  52 class L1I(L1_ICache):
  53     tag_latency = 1
  54     data_latency = 1
  55     response_latency = 1
  56     mshrs = 4
  57     tgts_per_mshr = 8
  58     size = '48kB'
  59     assoc = 3
  60
  61
  62 class L1D(L1_DCache):
  63     tag_latency = 2
  64     data_latency = 2
  65     response_latency = 1
  66     mshrs = 16
  67     tgts_per_mshr = 16
  68     size = '32kB'
  69     assoc = 2
  70     write_buffers = 16
  71
  72
  73 class WalkCache(PageTableWalkerCache):
  74     tag_latency = 4
  75     data_latency = 4
  76     response_latency = 4
  77     mshrs = 6
  78     tgts_per_mshr = 8
  79     size = '1kB'
  80     assoc = 8
  81     write_buffers = 16
  82
  83
  84 class L2(L2Cache):
  85     tag_latency = 12
  86     data_latency = 12
  87     response_latency = 5
  88     mshrs = 32
  89     tgts_per_mshr = 8
  90     size = '1MB'
  91     assoc = 16
  92     write_buffers = 8
  93     clusivity='mostly_excl'
  94
  95
  96 class L3(Cache):
  97     size = '16MB'
  98     assoc = 16
  99     tag_latency = 20
 100     data_latency = 20
 101     response_latency = 20
 102     mshrs = 20
 103     tgts_per_mshr = 12
 104     clusivity='mostly_excl'
 105
 106
 107 class MemBus(SystemXBar):
 108     badaddr_responder = BadAddr(warn_access="warn")
 109     default = Self.badaddr_responder.pio
 110
 111
 112 class CpuCluster(SubSystem):
 113     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
 114                  cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
 115         super(CpuCluster, self).__init__()
 116         self._cpu_type = cpu_type
 117         self._l1i_type = l1i_type
 118         self._l1d_type = l1d_type
 119         self._wcache_type = wcache_type
 120         self._l2_type = l2_type
 121
 122         assert num_cpus > 0
 123
 124         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
 125         self.clk_domain = SrcClockDomain(clock=cpu_clock,
 126                                          voltage_domain=self.voltage_domain)
 127
 128         self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
 129                                      clk_domain=self.clk_domain)
 130                       for idx in range(num_cpus) ]
 131
 132         for cpu in self.cpus:
 133             cpu.createThreads()
 134             cpu.createInterruptController()
 135             cpu.socket_id = system.numCpuClusters()
 136         system.addCpuCluster(self, num_cpus)
 137
 138     def requireCaches(self):
 139         return self._cpu_type.require_caches()
 140
 141     def memoryMode(self):
 142         return self._cpu_type.memory_mode()
 143
 144     def addL1(self):
 145         for cpu in self.cpus:
 146             l1i = None if self._l1i_type is None else self._l1i_type()
 147             l1d = None if self._l1d_type is None else self._l1d_type()
 148             iwc = None if self._wcache_type is None else self._wcache_type()
 149             dwc = None if self._wcache_type is None else self._wcache_type()
 150             cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
 151
 152     def addL2(self, clk_domain):
 153         if self._l2_type is None:
 154             return
 155         self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
 156         self.l2 = self._l2_type()
 157         for cpu in self.cpus:
 158             cpu.connectAllPorts(self.toL2Bus)
 159         self.toL2Bus.master = self.l2.cpu_side
 160
 161     def connectMemSide(self, bus):
 162         bus.slave
 163         try:
 164             self.l2.mem_side = bus.slave
 165         except AttributeError:
 166             for cpu in self.cpus:
 167                 cpu.connectAllPorts(bus)
 168
 169
 170 class AtomicCluster(CpuCluster):
 171     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 172         cpu_config = [ ObjectList.cpu_list.get("AtomicSimpleCPU"), None,
 173                        None, None, None ]
 174         super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
 175                                             cpu_voltage, *cpu_config)
 176     def addL1(self):
 177         pass
 178
 179 class KvmCluster(CpuCluster):
 180     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
 181         cpu_config = [ ObjectList.cpu_list.get("ArmV8KvmCPU"), None, None,
 182             None, None ]
 183         super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
 184                                          cpu_voltage, *cpu_config)
 185     def addL1(self):
 186         pass
 187
 188
 189 def simpleSystem(BaseSystem, caches, mem_size, platform=None, **kwargs):
 190     """
 191     Create a simple system example.  The base class in configurable so
 192     that it is possible (e.g) to link the platform (hardware configuration)
 193     with a baremetal ArmSystem or with a LinuxArmSystem.
 194     """
 195     class SimpleSystem(BaseSystem):
 196         cache_line_size = 64
 197
 198         def __init__(self, caches, mem_size, platform=None, **kwargs):
 199             super(SimpleSystem, self).__init__(**kwargs)
 200
 201             self.voltage_domain = VoltageDomain(voltage="1.0V")
 202             self.clk_domain = SrcClockDomain(
 203                 clock="1GHz",
 204                 voltage_domain=Parent.voltage_domain)
 205
 206             if platform is None:
 207                 self.realview = VExpress_GEM5_V1()
 208             else:
 209                 self.realview = platform
 210
 211             if hasattr(self.realview.gic, 'cpu_addr'):
 212                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 213             self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 214
 215             self.membus = MemBus()
 216
 217             self.intrctrl = IntrControl()
 218             self.terminal = Terminal()
 219             self.vncserver = VncServer()
 220
 221             self.iobus = IOXBar()
 222             # CPUs->PIO
 223             self.iobridge = Bridge(delay='50ns')
 224             # Device DMA -> MEM
 225             mem_range = self.realview._mem_regions[0]
 226             assert long(mem_range.size()) >= long(Addr(mem_size))
 227             self.mem_ranges = [
 228                 AddrRange(start=mem_range.start, size=mem_size) ]
 229
 230             self._caches = caches
 231             if self._caches:
 232                 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
 233             else:
 234                 self.dmabridge = Bridge(delay='50ns',
 235                                         ranges=[self.mem_ranges[0]])
 236
 237             self._pci_devices = 0
 238             self._clusters = []
 239             self._num_cpus = 0
 240
 241         def attach_pci(self, dev):
 242             dev.pci_bus, dev.pci_dev, dev.pci_func = \
 243                 (0, self._pci_devices + 1, 0)
 244             self._pci_devices += 1
 245             self.realview.attachPciDevice(dev, self.iobus)
 246
 247         def connect(self):
 248             self.iobridge.master = self.iobus.slave
 249             self.iobridge.slave = self.membus.master
 250
 251             if self._caches:
 252                 self.iocache.mem_side = self.membus.slave
 253                 self.iocache.cpu_side = self.iobus.master
 254             else:
 255                 self.dmabridge.master = self.membus.slave
 256                 self.dmabridge.slave = self.iobus.master
 257
 258             if hasattr(self.realview.gic, 'cpu_addr'):
 259                 self.gic_cpu_addr = self.realview.gic.cpu_addr
 260             self.realview.attachOnChipIO(self.membus, self.iobridge)
 261             self.realview.attachIO(self.iobus)
 262             self.system_port = self.membus.slave
 263
 264         def numCpuClusters(self):
 265             return len(self._clusters)
 266
 267         def addCpuCluster(self, cpu_cluster, num_cpus):
 268             assert cpu_cluster not in self._clusters
 269             assert num_cpus > 0
 270             self._clusters.append(cpu_cluster)
 271             self._num_cpus += num_cpus
 272
 273         def numCpus(self):
 274             return self._num_cpus
 275
 276         def addCaches(self, need_caches, last_cache_level):
 277             if not need_caches:
 278                 # connect each cluster to the memory hierarchy
 279                 for cluster in self._clusters:
 280                     cluster.connectMemSide(self.membus)
 281                 return
 282
 283             cluster_mem_bus = self.membus
 284             assert last_cache_level >= 1 and last_cache_level <= 3
 285             for cluster in self._clusters:
 286                 cluster.addL1()
 287             if last_cache_level > 1:
 288                 for cluster in self._clusters:
 289                     cluster.addL2(cluster.clk_domain)
 290             if last_cache_level > 2:
 291                 max_clock_cluster = max(self._clusters,
 292                                         key=lambda c: c.clk_domain.clock[0])
 293                 self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
 294                 self.toL3Bus = L2XBar(width=64)
 295                 self.toL3Bus.master = self.l3.cpu_side
 296                 self.l3.mem_side = self.membus.slave
 297                 cluster_mem_bus = self.toL3Bus
 298
 299             # connect each cluster to the memory hierarchy
 300             for cluster in self._clusters:
 301                 cluster.connectMemSide(cluster_mem_bus)
 302
 303     return SimpleSystem(caches, mem_size, platform, **kwargs)