1 # Copyright (c) 2016-2017 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
39 # System components used by the bigLITTLE.py configuration script
41 from __future__
import print_function
42 from __future__
import absolute_import
45 from m5
.objects
import *
46 m5
.util
.addToPath('../../')
47 from common
.Caches
import *
48 from common
import CpuConfig
50 have_kvm
= "ArmV8KvmCPU" in CpuConfig
.cpu_names()
73 class WalkCache(PageTableWalkerCache
):
93 clusivity
='mostly_excl'
101 response_latency
= 20
104 clusivity
='mostly_excl'
107 class MemBus(SystemXBar
):
108 badaddr_responder
= BadAddr(warn_access
="warn")
109 default
= Self
.badaddr_responder
.pio
112 class CpuCluster(SubSystem
):
113 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
,
114 cpu_type
, l1i_type
, l1d_type
, wcache_type
, l2_type
):
115 super(CpuCluster
, self
).__init
__()
116 self
._cpu
_type
= cpu_type
117 self
._l1i
_type
= l1i_type
118 self
._l1d
_type
= l1d_type
119 self
._wcache
_type
= wcache_type
120 self
._l2_type
= l2_type
124 self
.voltage_domain
= VoltageDomain(voltage
=cpu_voltage
)
125 self
.clk_domain
= SrcClockDomain(clock
=cpu_clock
,
126 voltage_domain
=self
.voltage_domain
)
128 self
.cpus
= [ self
._cpu
_type
(cpu_id
=system
.numCpus() + idx
,
129 clk_domain
=self
.clk_domain
)
130 for idx
in range(num_cpus
) ]
132 for cpu
in self
.cpus
:
134 cpu
.createInterruptController()
135 cpu
.socket_id
= system
.numCpuClusters()
136 system
.addCpuCluster(self
, num_cpus
)
138 def requireCaches(self
):
139 return self
._cpu
_type
.require_caches()
141 def memoryMode(self
):
142 return self
._cpu
_type
.memory_mode()
145 for cpu
in self
.cpus
:
146 l1i
= None if self
._l1i
_type
is None else self
._l1i
_type
()
147 l1d
= None if self
._l1d
_type
is None else self
._l1d
_type
()
148 iwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
149 dwc
= None if self
._wcache
_type
is None else self
._wcache
_type
()
150 cpu
.addPrivateSplitL1Caches(l1i
, l1d
, iwc
, dwc
)
152 def addL2(self
, clk_domain
):
153 if self
._l2_type
is None:
155 self
.toL2Bus
= L2XBar(width
=64, clk_domain
=clk_domain
)
156 self
.l2
= self
._l2_type
()
157 for cpu
in self
.cpus
:
158 cpu
.connectAllPorts(self
.toL2Bus
)
159 self
.toL2Bus
.master
= self
.l2
.cpu_side
161 def connectMemSide(self
, bus
):
164 self
.l2
.mem_side
= bus
.slave
165 except AttributeError:
166 for cpu
in self
.cpus
:
167 cpu
.connectAllPorts(bus
)
170 class AtomicCluster(CpuCluster
):
171 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
172 cpu_config
= [ CpuConfig
.get("AtomicSimpleCPU"), None, None, None, None ]
173 super(AtomicCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
174 cpu_voltage
, *cpu_config
)
178 class KvmCluster(CpuCluster
):
179 def __init__(self
, system
, num_cpus
, cpu_clock
, cpu_voltage
="1.0V"):
180 cpu_config
= [ CpuConfig
.get("ArmV8KvmCPU"), None, None, None, None ]
181 super(KvmCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
182 cpu_voltage
, *cpu_config
)
187 class SimpleSystem(LinuxArmSystem
):
190 def __init__(self
, caches
, mem_size
, **kwargs
):
191 super(SimpleSystem
, self
).__init
__(**kwargs
)
193 self
.voltage_domain
= VoltageDomain(voltage
="1.0V")
194 self
.clk_domain
= SrcClockDomain(clock
="1GHz",
195 voltage_domain
=Parent
.voltage_domain
)
197 self
.realview
= VExpress_GEM5_V1()
199 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
200 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
202 self
.membus
= MemBus()
204 self
.intrctrl
= IntrControl()
205 self
.terminal
= Terminal()
206 self
.vncserver
= VncServer()
208 self
.iobus
= IOXBar()
210 self
.iobridge
= Bridge(delay
='50ns')
212 mem_range
= self
.realview
._mem
_regions
[0]
213 assert long(mem_range
.size()) >= long(Addr(mem_size
))
214 self
.mem_ranges
= [ AddrRange(start
=mem_range
.start
, size
=mem_size
) ]
215 self
._caches
= caches
217 self
.iocache
= IOCache(addr_ranges
=[self
.mem_ranges
[0]])
219 self
.dmabridge
= Bridge(delay
='50ns',
220 ranges
=[self
.mem_ranges
[0]])
222 self
._pci
_devices
= 0
226 def attach_pci(self
, dev
):
227 dev
.pci_bus
, dev
.pci_dev
, dev
.pci_func
= (0, self
._pci
_devices
+ 1, 0)
228 self
._pci
_devices
+= 1
229 self
.realview
.attachPciDevice(dev
, self
.iobus
)
232 self
.iobridge
.master
= self
.iobus
.slave
233 self
.iobridge
.slave
= self
.membus
.master
236 self
.iocache
.mem_side
= self
.membus
.slave
237 self
.iocache
.cpu_side
= self
.iobus
.master
239 self
.dmabridge
.master
= self
.membus
.slave
240 self
.dmabridge
.slave
= self
.iobus
.master
242 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
243 self
.realview
.attachOnChipIO(self
.membus
, self
.iobridge
)
244 self
.realview
.attachIO(self
.iobus
)
245 self
.system_port
= self
.membus
.slave
247 def numCpuClusters(self
):
248 return len(self
._clusters
)
250 def addCpuCluster(self
, cpu_cluster
, num_cpus
):
251 assert cpu_cluster
not in self
._clusters
253 self
._clusters
.append(cpu_cluster
)
254 self
._num
_cpus
+= num_cpus
257 return self
._num
_cpus
259 def addCaches(self
, need_caches
, last_cache_level
):
261 # connect each cluster to the memory hierarchy
262 for cluster
in self
._clusters
:
263 cluster
.connectMemSide(self
.membus
)
266 cluster_mem_bus
= self
.membus
267 assert last_cache_level
>= 1 and last_cache_level
<= 3
268 for cluster
in self
._clusters
:
270 if last_cache_level
> 1:
271 for cluster
in self
._clusters
:
272 cluster
.addL2(cluster
.clk_domain
)
273 if last_cache_level
> 2:
274 max_clock_cluster
= max(self
._clusters
,
275 key
=lambda c
: c
.clk_domain
.clock
[0])
276 self
.l3
= L3(clk_domain
=max_clock_cluster
.clk_domain
)
277 self
.toL3Bus
= L2XBar(width
=64)
278 self
.toL3Bus
.master
= self
.l3
.cpu_side
279 self
.l3
.mem_side
= self
.membus
.slave
280 cluster_mem_bus
= self
.toL3Bus
282 # connect each cluster to the memory hierarchy
283 for cluster
in self
._clusters
:
284 cluster
.connectMemSide(cluster_mem_bus
)