1 # Copyright (c) 2016-2017, 2019 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # This is an example configuration script for full system simulation of
37 # a generic ARM bigLITTLE system.
40 from __future__
import print_function
41 from __future__
import absolute_import
48 from m5
.objects
import *
50 m5
.util
.addToPath("../../")
52 from common
import FSConfig
53 from common
import SysPaths
54 from common
import ObjectList
55 from common
import Options
56 from common
.cores
.arm
import ex5_big
, ex5_LITTLE
59 from devices
import AtomicCluster
, KvmCluster
, FastmodelCluster
62 default_disk
= 'aarch64-ubuntu-trusty-headless.img'
63 default_rcs
= 'bootscript.rcS'
65 default_mem_size
= "2GB"
68 """Helper function to convert a latency from string format to Ticks"""
70 return m5
.ticks
.fromSeconds(m5
.util
.convert
.anyToLatency(value
))
72 def _using_pdes(root
):
73 """Determine if the simulator is using multiple parallel event queues"""
75 for obj
in root
.descendants():
76 if not m5
.proxy
.isproxy(obj
.eventq_index
) and \
77 obj
.eventq_index
!= root
.eventq_index
:
83 class BigCluster(devices
.CpuCluster
):
84 def __init__(self
, system
, num_cpus
, cpu_clock
,
86 cpu_config
= [ ObjectList
.cpu_list
.get("O3_ARM_v7a_3"),
87 devices
.L1I
, devices
.L1D
, devices
.WalkCache
, devices
.L2
]
88 super(BigCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
89 cpu_voltage
, *cpu_config
)
91 class LittleCluster(devices
.CpuCluster
):
92 def __init__(self
, system
, num_cpus
, cpu_clock
,
94 cpu_config
= [ ObjectList
.cpu_list
.get("MinorCPU"), devices
.L1I
,
95 devices
.L1D
, devices
.WalkCache
, devices
.L2
]
96 super(LittleCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
97 cpu_voltage
, *cpu_config
)
99 class Ex5BigCluster(devices
.CpuCluster
):
100 def __init__(self
, system
, num_cpus
, cpu_clock
,
102 cpu_config
= [ ObjectList
.cpu_list
.get("ex5_big"), ex5_big
.L1I
,
103 ex5_big
.L1D
, ex5_big
.WalkCache
, ex5_big
.L2
]
104 super(Ex5BigCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
105 cpu_voltage
, *cpu_config
)
107 class Ex5LittleCluster(devices
.CpuCluster
):
108 def __init__(self
, system
, num_cpus
, cpu_clock
,
110 cpu_config
= [ ObjectList
.cpu_list
.get("ex5_LITTLE"),
111 ex5_LITTLE
.L1I
, ex5_LITTLE
.L1D
, ex5_LITTLE
.WalkCache
,
113 super(Ex5LittleCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
114 cpu_voltage
, *cpu_config
)
116 def createSystem(caches
, kernel
, bootscript
, machine_type
="VExpress_GEM5",
117 disks
=[], mem_size
=default_mem_size
, bootloader
=None):
118 platform
= ObjectList
.platform_list
.get(machine_type
)
119 m5
.util
.inform("Simulated platform: %s", platform
.__name
__)
121 sys
= devices
.simpleSystem(ArmSystem
,
122 caches
, mem_size
, platform(),
124 object_file
=SysPaths
.binary(kernel
)),
127 sys
.mem_ctrls
= [ SimpleMemory(range=r
, port
=sys
.membus
.master
)
128 for r
in sys
.mem_ranges
]
134 def cow_disk(image_file
):
135 image
= CowDiskImage()
136 image
.child
.image_file
= SysPaths
.disk(image_file
)
139 sys
.disk_images
= [ cow_disk(f
) for f
in disks
]
140 sys
.pci_vio_block
= [ PciVirtIO(vio
=VirtIOBlock(image
=img
))
141 for img
in sys
.disk_images
]
142 for dev
in sys
.pci_vio_block
:
145 sys
.realview
.setupBootLoader(sys
, SysPaths
.binary
, bootloader
)
150 "atomic" : (AtomicCluster
, AtomicCluster
),
151 "timing" : (BigCluster
, LittleCluster
),
152 "exynos" : (Ex5BigCluster
, Ex5LittleCluster
),
155 # Only add the KVM CPU if it has been compiled into gem5
157 cpu_types
["kvm"] = (KvmCluster
, KvmCluster
)
159 # Only add the FastModel CPU if it has been compiled into gem5
160 if devices
.have_fastmodel
:
161 cpu_types
["fastmodel"] = (FastmodelCluster
, FastmodelCluster
)
163 def addOptions(parser
):
164 parser
.add_argument("--restore-from", type=str, default
=None,
165 help="Restore from checkpoint")
166 parser
.add_argument("--dtb", type=str, default
=None,
167 help="DTB file to load")
168 parser
.add_argument("--kernel", type=str, required
=True,
170 parser
.add_argument("--root", type=str, default
="/dev/vda1",
171 help="Specify the kernel CLI root= argument")
172 parser
.add_argument("--machine-type", type=str,
173 choices
=ObjectList
.platform_list
.get_names(),
174 default
="VExpress_GEM5",
175 help="Hardware platform class")
176 parser
.add_argument("--disk", action
="append", type=str, default
=[],
177 help="Disks to instantiate")
178 parser
.add_argument("--bootscript", type=str, default
=default_rcs
,
179 help="Linux bootscript")
180 parser
.add_argument("--cpu-type", type=str, choices
=list(cpu_types
.keys()),
182 help="CPU simulation mode. Default: %(default)s")
183 parser
.add_argument("--kernel-init", type=str, default
="/sbin/init",
184 help="Override init")
185 parser
.add_argument("--big-cpus", type=int, default
=1,
186 help="Number of big CPUs to instantiate")
187 parser
.add_argument("--little-cpus", type=int, default
=1,
188 help="Number of little CPUs to instantiate")
189 parser
.add_argument("--caches", action
="store_true", default
=False,
190 help="Instantiate caches")
191 parser
.add_argument("--last-cache-level", type=int, default
=2,
192 help="Last level of caches (e.g. 3 for L3)")
193 parser
.add_argument("--big-cpu-clock", type=str, default
="2GHz",
194 help="Big CPU clock frequency")
195 parser
.add_argument("--little-cpu-clock", type=str, default
="1GHz",
196 help="Little CPU clock frequency")
197 parser
.add_argument("--sim-quantum", type=str, default
="1ms",
198 help="Simulation quantum for parallel simulation. " \
199 "Default: %(default)s")
200 parser
.add_argument("--mem-size", type=str, default
=default_mem_size
,
201 help="System memory size")
202 parser
.add_argument("--kernel-cmd", type=str, default
=None,
203 help="Custom Linux kernel command")
204 parser
.add_argument("--bootloader", action
="append",
205 help="executable file that runs before the --kernel")
206 parser
.add_argument("-P", "--param", action
="append", default
=[],
207 help="Set a SimObject parameter relative to the root node. "
208 "An extended Python multi range slicing syntax can be used "
209 "for arrays. For example: "
210 "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
211 "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
212 "Direct parameters of the root object are not accessible, "
213 "only parameters of its children.")
214 parser
.add_argument("--vio-9p", action
="store_true",
215 help=Options
.vio_9p_help
)
219 m5
.ticks
.fixGlobalFrequency()
222 "earlyprintk=pl011,0x1c090000",
227 "mem=%s" % options
.mem_size
,
228 "root=%s" % options
.root
,
230 "init=%s" % options
.kernel_init
,
234 root
= Root(full_system
=True)
236 disks
= [default_disk
] if len(options
.disk
) == 0 else options
.disk
237 system
= createSystem(options
.caches
,
240 options
.machine_type
,
242 mem_size
=options
.mem_size
,
243 bootloader
=options
.bootloader
)
246 if options
.kernel_cmd
:
247 system
.workload
.command_line
= options
.kernel_cmd
249 system
.workload
.command_line
= " ".join(kernel_cmd
)
251 if options
.big_cpus
+ options
.little_cpus
== 0:
252 m5
.util
.panic("Empty CPU clusters")
254 big_model
, little_model
= cpu_types
[options
.cpu_type
]
258 if options
.big_cpus
> 0:
259 system
.bigCluster
= big_model(system
, options
.big_cpus
,
260 options
.big_cpu_clock
)
261 system
.mem_mode
= system
.bigCluster
.memoryMode()
262 all_cpus
+= system
.bigCluster
.cpus
265 if options
.little_cpus
> 0:
266 system
.littleCluster
= little_model(system
, options
.little_cpus
,
267 options
.little_cpu_clock
)
268 system
.mem_mode
= system
.littleCluster
.memoryMode()
269 all_cpus
+= system
.littleCluster
.cpus
271 # Figure out the memory mode
272 if options
.big_cpus
> 0 and options
.little_cpus
> 0 and \
273 system
.bigCluster
.memoryMode() != system
.littleCluster
.memoryMode():
274 m5
.util
.panic("Memory mode missmatch among CPU clusters")
278 system
.addCaches(options
.caches
, options
.last_cache_level
)
279 if not options
.caches
:
280 if options
.big_cpus
> 0 and system
.bigCluster
.requireCaches():
281 m5
.util
.panic("Big CPU model requires caches")
282 if options
.little_cpus
> 0 and system
.littleCluster
.requireCaches():
283 m5
.util
.panic("Little CPU model requires caches")
285 # Create a KVM VM and do KVM-specific configuration
286 if issubclass(big_model
, KvmCluster
):
287 _build_kvm(system
, all_cpus
)
290 if options
.dtb
is not None:
291 system
.workload
.dtb_filename
= SysPaths
.binary(options
.dtb
)
293 system
.workload
.dtb_filename
= \
294 os
.path
.join(m5
.options
.outdir
, 'system.dtb')
295 system
.generateDtb(system
.workload
.dtb_filename
)
297 if devices
.have_fastmodel
and issubclass(big_model
, FastmodelCluster
):
298 from m5
import arm_fast_model
as fm
, systemc
as sc
299 # setup FastModels for simulation
300 fm
.setup_simulation("cortexa76")
302 root
.systemc_kernel
= m5
.objects
.SystemC_Kernel()
303 m5
.tlm
.tlm_global_quantum_instance().set(
304 sc
.sc_time(10000.0 / 100000000.0, sc
.sc_time
.SC_SEC
))
307 FSConfig
.attach_9p(system
.realview
, system
.iobus
)
311 def _build_kvm(system
, cpus
):
312 system
.kvm_vm
= KvmVM()
314 # Assign KVM CPUs to their own event queues / threads. This
315 # has to be done after creating caches and other child objects
316 # since these mustn't inherit the CPU event queue.
320 for idx
, cpu
in enumerate(cpus
):
321 # Child objects usually inherit the parent's event
322 # queue. Override that and use the same event queue for
324 for obj
in cpu
.descendants():
325 obj
.eventq_index
= device_eq
326 cpu
.eventq_index
= first_cpu_eq
+ idx
330 def instantiate(options
, checkpoint_dir
=None):
331 # Setup the simulation quantum if we are running in PDES-mode
332 # (e.g., when using KVM)
333 root
= Root
.getInstance()
334 if root
and _using_pdes(root
):
335 m5
.util
.inform("Running in PDES mode with a %s simulation quantum.",
337 root
.sim_quantum
= _to_ticks(options
.sim_quantum
)
339 # Get and load from the chkpt or simpoint checkpoint
340 if options
.restore_from
:
341 if checkpoint_dir
and not os
.path
.isabs(options
.restore_from
):
342 cpt
= os
.path
.join(checkpoint_dir
, options
.restore_from
)
344 cpt
= options
.restore_from
346 m5
.util
.inform("Restoring from checkpoint %s", cpt
)
352 def run(checkpoint_dir
=m5
.options
.outdir
):
353 # start simulation (and drop checkpoints when requested)
355 event
= m5
.simulate()
356 exit_msg
= event
.getCause()
357 if exit_msg
== "checkpoint":
358 print("Dropping checkpoint at tick %d" % m5
.curTick())
359 cpt_dir
= os
.path
.join(checkpoint_dir
, "cpt.%d" % m5
.curTick())
360 m5
.checkpoint(cpt_dir
)
361 print("Checkpoint done.")
363 print(exit_msg
, " @ ", m5
.curTick())
366 sys
.exit(event
.getCode())
370 parser
= argparse
.ArgumentParser(
371 description
="Generic ARM big.LITTLE configuration")
373 options
= parser
.parse_args()
374 root
= build(options
)
375 root
.apply_config(options
.param
)
380 if __name__
== "__m5_main__":