1 # Copyright (c) 2016-2017, 2019 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Gabor Dozsa
39 # This is an example configuration script for full system simulation of
40 # a generic ARM bigLITTLE system.
43 from __future__
import print_function
44 from __future__
import absolute_import
51 from m5
.objects
import *
53 m5
.util
.addToPath("../../")
55 from common
import SysPaths
56 from common
import ObjectList
57 from common
import PlatformConfig
58 from common
.cores
.arm
import ex5_big
, ex5_LITTLE
61 from devices
import AtomicCluster
, KvmCluster
64 default_disk
= 'aarch64-ubuntu-trusty-headless.img'
65 default_rcs
= 'bootscript.rcS'
67 default_mem_size
= "2GB"
70 """Helper function to convert a latency from string format to Ticks"""
72 return m5
.ticks
.fromSeconds(m5
.util
.convert
.anyToLatency(value
))
74 def _using_pdes(root
):
75 """Determine if the simulator is using multiple parallel event queues"""
77 for obj
in root
.descendants():
78 if not m5
.proxy
.isproxy(obj
.eventq_index
) and \
79 obj
.eventq_index
!= root
.eventq_index
:
85 class BigCluster(devices
.CpuCluster
):
86 def __init__(self
, system
, num_cpus
, cpu_clock
,
88 cpu_config
= [ ObjectList
.cpu_list
.get("O3_ARM_v7a_3"),
89 devices
.L1I
, devices
.L1D
, devices
.WalkCache
, devices
.L2
]
90 super(BigCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
91 cpu_voltage
, *cpu_config
)
93 class LittleCluster(devices
.CpuCluster
):
94 def __init__(self
, system
, num_cpus
, cpu_clock
,
96 cpu_config
= [ ObjectList
.cpu_list
.get("MinorCPU"), devices
.L1I
,
97 devices
.L1D
, devices
.WalkCache
, devices
.L2
]
98 super(LittleCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
99 cpu_voltage
, *cpu_config
)
101 class Ex5BigCluster(devices
.CpuCluster
):
102 def __init__(self
, system
, num_cpus
, cpu_clock
,
104 cpu_config
= [ ObjectList
.cpu_list
.get("ex5_big"), ex5_big
.L1I
,
105 ex5_big
.L1D
, ex5_big
.WalkCache
, ex5_big
.L2
]
106 super(Ex5BigCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
107 cpu_voltage
, *cpu_config
)
109 class Ex5LittleCluster(devices
.CpuCluster
):
110 def __init__(self
, system
, num_cpus
, cpu_clock
,
112 cpu_config
= [ ObjectList
.cpu_list
.get("ex5_LITTLE"),
113 ex5_LITTLE
.L1I
, ex5_LITTLE
.L1D
, ex5_LITTLE
.WalkCache
,
115 super(Ex5LittleCluster
, self
).__init
__(system
, num_cpus
, cpu_clock
,
116 cpu_voltage
, *cpu_config
)
118 def createSystem(caches
, kernel
, bootscript
,
119 machine_type
="VExpress_GEM5", disks
=[]):
120 platform
= PlatformConfig
.get(machine_type
)
121 m5
.util
.inform("Simulated platform: %s", platform
.__name
__)
123 sys
= devices
.SimpleSystem(caches
, default_mem_size
, platform(),
124 kernel
=SysPaths
.binary(kernel
),
127 sys
.mem_ctrls
= [ SimpleMemory(range=r
, port
=sys
.membus
.master
)
128 for r
in sys
.mem_ranges
]
134 def cow_disk(image_file
):
135 image
= CowDiskImage()
136 image
.child
.image_file
= SysPaths
.disk(image_file
)
139 sys
.disk_images
= [ cow_disk(f
) for f
in disks
]
140 sys
.pci_vio_block
= [ PciVirtIO(vio
=VirtIOBlock(image
=img
))
141 for img
in sys
.disk_images
]
142 for dev
in sys
.pci_vio_block
:
145 sys
.realview
.setupBootLoader(sys
.membus
, sys
, SysPaths
.binary
)
150 "atomic" : (AtomicCluster
, AtomicCluster
),
151 "timing" : (BigCluster
, LittleCluster
),
152 "exynos" : (Ex5BigCluster
, Ex5LittleCluster
),
155 # Only add the KVM CPU if it has been compiled into gem5
157 cpu_types
["kvm"] = (KvmCluster
, KvmCluster
)
160 def addOptions(parser
):
161 parser
.add_argument("--restore-from", type=str, default
=None,
162 help="Restore from checkpoint")
163 parser
.add_argument("--dtb", type=str, default
=None,
164 help="DTB file to load")
165 parser
.add_argument("--kernel", type=str, required
=True,
167 parser
.add_argument("--root", type=str, default
="/dev/vda1",
168 help="Specify the kernel CLI root= argument")
169 parser
.add_argument("--machine-type", type=str,
170 choices
=PlatformConfig
.platform_names(),
171 default
="VExpress_GEM5",
172 help="Hardware platform class")
173 parser
.add_argument("--disk", action
="append", type=str, default
=[],
174 help="Disks to instantiate")
175 parser
.add_argument("--bootscript", type=str, default
=default_rcs
,
176 help="Linux bootscript")
177 parser
.add_argument("--cpu-type", type=str, choices
=cpu_types
.keys(),
179 help="CPU simulation mode. Default: %(default)s")
180 parser
.add_argument("--kernel-init", type=str, default
="/sbin/init",
181 help="Override init")
182 parser
.add_argument("--big-cpus", type=int, default
=1,
183 help="Number of big CPUs to instantiate")
184 parser
.add_argument("--little-cpus", type=int, default
=1,
185 help="Number of little CPUs to instantiate")
186 parser
.add_argument("--caches", action
="store_true", default
=False,
187 help="Instantiate caches")
188 parser
.add_argument("--last-cache-level", type=int, default
=2,
189 help="Last level of caches (e.g. 3 for L3)")
190 parser
.add_argument("--big-cpu-clock", type=str, default
="2GHz",
191 help="Big CPU clock frequency")
192 parser
.add_argument("--little-cpu-clock", type=str, default
="1GHz",
193 help="Little CPU clock frequency")
194 parser
.add_argument("--sim-quantum", type=str, default
="1ms",
195 help="Simulation quantum for parallel simulation. " \
196 "Default: %(default)s")
197 parser
.add_argument("-P", "--param", action
="append", default
=[],
198 help="Set a SimObject parameter relative to the root node. "
199 "An extended Python multi range slicing syntax can be used "
200 "for arrays. For example: "
201 "'system.cpu[0,1,3:8:2].max_insts_all_threads = 42' "
202 "sets max_insts_all_threads for cpus 0, 1, 3, 5 and 7 "
203 "Direct parameters of the root object are not accessible, "
204 "only parameters of its children.")
208 m5
.ticks
.fixGlobalFrequency()
211 "earlyprintk=pl011,0x1c090000",
216 "mem=%s" % default_mem_size
,
217 "root=%s" % options
.root
,
219 "init=%s" % options
.kernel_init
,
223 root
= Root(full_system
=True)
225 disks
= [default_disk
] if len(options
.disk
) == 0 else options
.disk
226 system
= createSystem(options
.caches
,
229 options
.machine_type
,
233 system
.boot_osflags
= " ".join(kernel_cmd
)
235 if options
.big_cpus
+ options
.little_cpus
== 0:
236 m5
.util
.panic("Empty CPU clusters")
238 big_model
, little_model
= cpu_types
[options
.cpu_type
]
242 if options
.big_cpus
> 0:
243 system
.bigCluster
= big_model(system
, options
.big_cpus
,
244 options
.big_cpu_clock
)
245 system
.mem_mode
= system
.bigCluster
.memoryMode()
246 all_cpus
+= system
.bigCluster
.cpus
249 if options
.little_cpus
> 0:
250 system
.littleCluster
= little_model(system
, options
.little_cpus
,
251 options
.little_cpu_clock
)
252 system
.mem_mode
= system
.littleCluster
.memoryMode()
253 all_cpus
+= system
.littleCluster
.cpus
255 # Figure out the memory mode
256 if options
.big_cpus
> 0 and options
.little_cpus
> 0 and \
257 system
.bigCluster
.memoryMode() != system
.littleCluster
.memoryMode():
258 m5
.util
.panic("Memory mode missmatch among CPU clusters")
262 system
.addCaches(options
.caches
, options
.last_cache_level
)
263 if not options
.caches
:
264 if options
.big_cpus
> 0 and system
.bigCluster
.requireCaches():
265 m5
.util
.panic("Big CPU model requires caches")
266 if options
.little_cpus
> 0 and system
.littleCluster
.requireCaches():
267 m5
.util
.panic("Little CPU model requires caches")
269 # Create a KVM VM and do KVM-specific configuration
270 if issubclass(big_model
, KvmCluster
):
271 _build_kvm(system
, all_cpus
)
274 if options
.dtb
is not None:
275 system
.dtb_filename
= SysPaths
.binary(options
.dtb
)
277 system
.generateDtb(m5
.options
.outdir
, 'system.dtb')
281 def _build_kvm(system
, cpus
):
282 system
.kvm_vm
= KvmVM()
284 # Assign KVM CPUs to their own event queues / threads. This
285 # has to be done after creating caches and other child objects
286 # since these mustn't inherit the CPU event queue.
290 for idx
, cpu
in enumerate(cpus
):
291 # Child objects usually inherit the parent's event
292 # queue. Override that and use the same event queue for
294 for obj
in cpu
.descendants():
295 obj
.eventq_index
= device_eq
296 cpu
.eventq_index
= first_cpu_eq
+ idx
300 def instantiate(options
, checkpoint_dir
=None):
301 # Setup the simulation quantum if we are running in PDES-mode
302 # (e.g., when using KVM)
303 root
= Root
.getInstance()
304 if root
and _using_pdes(root
):
305 m5
.util
.inform("Running in PDES mode with a %s simulation quantum.",
307 root
.sim_quantum
= _to_ticks(options
.sim_quantum
)
309 # Get and load from the chkpt or simpoint checkpoint
310 if options
.restore_from
:
311 if checkpoint_dir
and not os
.path
.isabs(options
.restore_from
):
312 cpt
= os
.path
.join(checkpoint_dir
, options
.restore_from
)
314 cpt
= options
.restore_from
316 m5
.util
.inform("Restoring from checkpoint %s", cpt
)
322 def run(checkpoint_dir
=m5
.options
.outdir
):
323 # start simulation (and drop checkpoints when requested)
325 event
= m5
.simulate()
326 exit_msg
= event
.getCause()
327 if exit_msg
== "checkpoint":
328 print("Dropping checkpoint at tick %d" % m5
.curTick())
329 cpt_dir
= os
.path
.join(checkpoint_dir
, "cpt.%d" % m5
.curTick())
330 m5
.checkpoint(cpt_dir
)
331 print("Checkpoint done.")
333 print(exit_msg
, " @ ", m5
.curTick())
336 sys
.exit(event
.getCode())
340 parser
= argparse
.ArgumentParser(
341 description
="Generic ARM big.LITTLE configuration")
343 options
= parser
.parse_args()
344 root
= build(options
)
345 root
.apply_config(options
.param
)
350 if __name__
== "__m5_main__":