7b92c8db8dbd105a283359739d64eea4ca55a2b6
1 # Copyright (c) 2017 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
37 # Stephan Diestelhorst
39 # This configuration file extends the example ARM big.LITTLE(tm)
40 # with example power models.
42 from __future__
import print_function
48 from m5
.objects
import MathExprPowerModel
, PowerModel
50 import fs_bigLITTLE
as bL
53 class CpuPowerOn(MathExprPowerModel
):
54 # 2A per IPC, 3pA per cache miss
55 # and then convert to Watt
56 dyn
= "voltage * (2 * ipc + " \
57 "3 * 0.000000001 * dcache.overall_misses / sim_seconds)"
60 class CpuPowerOff(MathExprPowerModel
):
64 class CpuPowerModel(PowerModel
):
67 CpuPowerOff(), # CLK_GATED
68 CpuPowerOff(), # SRAM_RETENTION
72 class L2PowerOn(MathExprPowerModel
):
73 # Example to report l2 Cache overall_accesses
74 # The estimated power is converted to Watt and will vary based on the size of the cache
75 dyn
= "overall_accesses*0.000018000"
76 st
= "(voltage * 3)/10"
78 class L2PowerOff(MathExprPowerModel
):
82 class L2PowerModel(PowerModel
):
83 # Choose a power model for every power state
86 L2PowerOff(), # CLK_GATED
87 L2PowerOff(), # SRAM_RETENTION
93 parser
= argparse
.ArgumentParser(
94 description
="Generic ARM big.LITTLE configuration with "\
95 "example power models")
97 options
= parser
.parse_args()
99 if options
.cpu_type
!= "timing":
100 m5
.fatal("The power example script requires 'timing' CPUs.")
102 root
= bL
.build(options
)
104 # Wire up some example power models to the CPUs
105 for cpu
in root
.system
.descendants():
106 if not isinstance(cpu
, m5
.objects
.BaseCPU
):
109 cpu
.default_p_state
= "ON"
110 cpu
.power_model
= CpuPowerModel()
112 # Example power model for the L2 Cache of the bigCluster
113 for l2
in root
.system
.bigCluster
.l2
.descendants():
114 if not isinstance(l2
, m5
.objects
.Cache
):
117 l2
.default_p_state
= "ON"
118 l2
.power_model
= L2PowerModel()
120 bL
.instantiate(options
)
123 print("WARNING: The power numbers generated by this script are "
124 "examples. They are not representative of any particular "
125 "implementation or process.")
128 # Dumping stats periodically
129 m5
.stats
.periodicStatDump(m5
.ticks
.fromSeconds(0.1E-3))
133 if __name__
== "__m5_main__":