1 # Copyright (c) 2016-2017 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 # Authors: Andreas Sandberg
41 """This script is the syscall emulation example script from the ARM
42 Research Starter Kit on System Modeling. More information can be found
43 at: http://www.arm.com/ResearchEnablement/SystemModeling
46 from __future__
import print_function
47 from __future__
import absolute_import
51 from m5
.util
import addToPath
52 from m5
.objects
import *
56 m5
.util
.addToPath('../..')
58 from common
import ObjectList
59 from common
import MemConfig
60 from common
.cores
.arm
import HPI
66 # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
67 # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
68 # the cache class may be 'None' if the particular cache is not present.
70 "atomic" : ( AtomicSimpleCPU
, None, None, None, None),
72 devices
.L1I
, devices
.L1D
,
76 HPI
.HPI_ICache
, HPI
.HPI_DCache
,
82 class SimpleSeSystem(System
):
84 Example system class for syscall emulation mode
87 # Use a fixed cache line size of 64 bytes
90 def __init__(self
, args
, **kwargs
):
91 super(SimpleSeSystem
, self
).__init
__(**kwargs
)
93 # Setup book keeping to be able to use CpuClusters from the
98 # Create a voltage and clock domain for system components
99 self
.voltage_domain
= VoltageDomain(voltage
="3.3V")
100 self
.clk_domain
= SrcClockDomain(clock
="1GHz",
101 voltage_domain
=self
.voltage_domain
)
103 # Create the off-chip memory bus.
104 self
.membus
= SystemXBar()
106 # Wire up the system port that gem5 uses to load the kernel
107 # and to perform debug accesses.
108 self
.system_port
= self
.membus
.slave
111 # Add CPUs to the system. A cluster of CPUs typically have
112 # private L1 caches and a shared L2 cache.
113 self
.cpu_cluster
= devices
.CpuCluster(self
,
115 args
.cpu_freq
, "1.2V",
116 *cpu_types
[args
.cpu
])
118 # Create a cache hierarchy (unless we are simulating a
119 # functional CPU in atomic memory mode) for the CPU cluster
120 # and connect it to the shared memory bus.
121 if self
.cpu_cluster
.memoryMode() == "timing":
122 self
.cpu_cluster
.addL1()
123 self
.cpu_cluster
.addL2(self
.cpu_cluster
.clk_domain
)
124 self
.cpu_cluster
.connectMemSide(self
.membus
)
126 # Tell gem5 about the memory mode used by the CPUs we are
128 self
.mem_mode
= self
.cpu_cluster
.memoryMode()
130 def numCpuClusters(self
):
131 return len(self
._clusters
)
133 def addCpuCluster(self
, cpu_cluster
, num_cpus
):
134 assert cpu_cluster
not in self
._clusters
136 self
._clusters
.append(cpu_cluster
)
137 self
._num
_cpus
+= num_cpus
140 return self
._num
_cpus
142 def get_processes(cmd
):
143 """Interprets commands to run and returns a list of processes"""
147 for idx
, c
in enumerate(cmd
):
148 argv
= shlex
.split(c
)
150 process
= Process(pid
=100 + idx
, cwd
=cwd
, cmd
=argv
, executable
=argv
[0])
152 print("info: %d. command and arguments: %s" % (idx
+ 1, process
.cmd
))
153 multiprocesses
.append(process
)
155 return multiprocesses
159 ''' Create and configure the system object. '''
161 system
= SimpleSeSystem(args
)
163 # Tell components about the expected physical memory ranges. This
164 # is, for example, used by the MemConfig helper to determine where
165 # to map DRAMs in the physical address space.
166 system
.mem_ranges
= [ AddrRange(start
=0, size
=args
.mem_size
) ]
168 # Configure the off-chip memory system.
169 MemConfig
.config_mem(args
, system
)
171 # Parse the command line and get a list of Processes instances
172 # that we can pass to gem5.
173 processes
= get_processes(args
.commands_to_run
)
174 if len(processes
) != args
.num_cores
:
175 print("Error: Cannot map %d command(s) onto %d CPU(s)" %
176 (len(processes
), args
.num_cores
))
179 # Assign one workload to each CPU
180 for cpu
, workload
in zip(system
.cpu_cluster
.cpus
, processes
):
181 cpu
.workload
= workload
187 parser
= argparse
.ArgumentParser(epilog
=__doc__
)
189 parser
.add_argument("commands_to_run", metavar
="command(s)", nargs
='*',
190 help="Command(s) to run")
191 parser
.add_argument("--cpu", type=str, choices
=cpu_types
.keys(),
193 help="CPU model to use")
194 parser
.add_argument("--cpu-freq", type=str, default
="4GHz")
195 parser
.add_argument("--num-cores", type=int, default
=1,
196 help="Number of CPU cores")
197 parser
.add_argument("--mem-type", default
="DDR3_1600_8x8",
198 choices
=ObjectList
.mem_list
.get_names(),
199 help = "type of memory to use")
200 parser
.add_argument("--mem-channels", type=int, default
=2,
201 help = "number of memory channels")
202 parser
.add_argument("--mem-ranks", type=int, default
=None,
203 help = "number of memory ranks per channel")
204 parser
.add_argument("--mem-size", action
="store", type=str,
206 help="Specify the physical memory size")
208 args
= parser
.parse_args()
210 # Create a single root node for gem5's object hierarchy. There can
211 # only exist one root node in the simulator at any given
212 # time. Tell gem5 that we want to use syscall emulation mode
213 # instead of full system mode.
214 root
= Root(full_system
=False)
216 # Populate the root node with a system. A system corresponds to a
217 # single node with shared memory.
218 root
.system
= create(args
)
220 # Instantiate the C++ object hierarchy. After this point,
221 # SimObjects can't be instantiated anymore.
224 # Start the simulator. This gives control to the C++ world and
225 # starts the simulator. The returned event tells the simulation
226 # script why the simulator exited.
227 event
= m5
.simulate()
229 # Print the reason for the simulation exit. Some exit codes are
230 # requests for service (e.g., checkpoints) from the simulation
231 # script. We'll just ignore them here and exit.
232 print(event
.getCause(), " @ ", m5
.curTick())
233 sys
.exit(event
.getCode())
236 if __name__
== "__m5_main__":