configs/example/arm/starter_se.py

   1 # Copyright (c) 2016-2017 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
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   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
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  11 # modified or unmodified, in source code or in binary form.
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  14 # modification, are permitted provided that the following conditions are
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  21 # contributors may be used to endorse or promote products derived from
  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 #  Authors:  Andreas Sandberg
  37 #            Chuan Zhu
  38 #            Gabor Dozsa
  39 #
  40
  41 """This script is the syscall emulation example script from the ARM
  42 Research Starter Kit on System Modeling. More information can be found
  43 at: http://www.arm.com/ResearchEnablement/SystemModeling
  44 """
  45
  46 from __future__ import print_function
  47
  48 import os
  49 import m5
  50 from m5.util import addToPath
  51 from m5.objects import *
  52 import argparse
  53 import shlex
  54
  55 m5.util.addToPath('../..')
  56
  57 from common import MemConfig
  58 from common.cores.arm import HPI
  59
  60 import devices
  61
  62
  63
  64 # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
  65 # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
  66 # the cache class may be 'None' if the particular cache is not present.
  67 cpu_types = {
  68     "atomic" : ( AtomicSimpleCPU, None, None, None, None),
  69     "minor" : (MinorCPU,
  70                devices.L1I, devices.L1D,
  71                devices.WalkCache,
  72                devices.L2),
  73     "hpi" : ( HPI.HPI,
  74               HPI.HPI_ICache, HPI.HPI_DCache,
  75               HPI.HPI_WalkCache,
  76               HPI.HPI_L2)
  77 }
  78
  79
  80 class SimpleSeSystem(System):
  81     '''
  82     Example system class for syscall emulation mode
  83     '''
  84
  85     # Use a fixed cache line size of 64 bytes
  86     cache_line_size = 64
  87
  88     def __init__(self, args, **kwargs):
  89         super(SimpleSeSystem, self).__init__(**kwargs)
  90
  91         # Setup book keeping to be able to use CpuClusters from the
  92         # devices module.
  93         self._clusters = []
  94         self._num_cpus = 0
  95
  96         # Create a voltage and clock domain for system components
  97         self.voltage_domain = VoltageDomain(voltage="3.3V")
  98         self.clk_domain = SrcClockDomain(clock="1GHz",
  99                                          voltage_domain=self.voltage_domain)
 100
 101         # Create the off-chip memory bus.
 102         self.membus = SystemXBar()
 103
 104         # Wire up the system port that gem5 uses to load the kernel
 105         # and to perform debug accesses.
 106         self.system_port = self.membus.slave
 107
 108
 109         # Add CPUs to the system. A cluster of CPUs typically have
 110         # private L1 caches and a shared L2 cache.
 111         self.cpu_cluster = devices.CpuCluster(self,
 112                                               args.num_cores,
 113                                               args.cpu_freq, "1.2V",
 114                                               *cpu_types[args.cpu])
 115
 116         # Create a cache hierarchy (unless we are simulating a
 117         # functional CPU in atomic memory mode) for the CPU cluster
 118         # and connect it to the shared memory bus.
 119         if self.cpu_cluster.memoryMode() == "timing":
 120             self.cpu_cluster.addL1()
 121             self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
 122         self.cpu_cluster.connectMemSide(self.membus)
 123
 124         # Tell gem5 about the memory mode used by the CPUs we are
 125         # simulating.
 126         self.mem_mode = self.cpu_cluster.memoryMode()
 127
 128     def numCpuClusters(self):
 129         return len(self._clusters)
 130
 131     def addCpuCluster(self, cpu_cluster, num_cpus):
 132         assert cpu_cluster not in self._clusters
 133         assert num_cpus > 0
 134         self._clusters.append(cpu_cluster)
 135         self._num_cpus += num_cpus
 136
 137     def numCpus(self):
 138         return self._num_cpus
 139
 140 def get_processes(cmd):
 141     """Interprets commands to run and returns a list of processes"""
 142
 143     cwd = os.getcwd()
 144     multiprocesses = []
 145     for idx, c in enumerate(cmd):
 146         argv = shlex.split(c)
 147
 148         process = Process(pid=100 + idx, cwd=cwd, cmd=argv, executable=argv[0])
 149
 150         print("info: %d. command and arguments: %s" % (idx + 1, process.cmd))
 151         multiprocesses.append(process)
 152
 153     return multiprocesses
 154
 155
 156 def create(args):
 157     ''' Create and configure the system object. '''
 158
 159     system = SimpleSeSystem(args)
 160
 161     # Tell components about the expected physical memory ranges. This
 162     # is, for example, used by the MemConfig helper to determine where
 163     # to map DRAMs in the physical address space.
 164     system.mem_ranges = [ AddrRange(start=0, size=args.mem_size) ]
 165
 166     # Configure the off-chip memory system.
 167     MemConfig.config_mem(args, system)
 168
 169     # Parse the command line and get a list of Processes instances
 170     # that we can pass to gem5.
 171     processes = get_processes(args.commands_to_run)
 172     if len(processes) != args.num_cores:
 173         print("Error: Cannot map %d command(s) onto %d CPU(s)" %
 174               (len(processes), args.num_cores))
 175         sys.exit(1)
 176
 177     # Assign one workload to each CPU
 178     for cpu, workload in zip(system.cpu_cluster.cpus, processes):
 179         cpu.workload = workload
 180
 181     return system
 182
 183
 184 def main():
 185     parser = argparse.ArgumentParser(epilog=__doc__)
 186
 187     parser.add_argument("commands_to_run", metavar="command(s)", nargs='*',
 188                         help="Command(s) to run")
 189     parser.add_argument("--cpu", type=str, choices=cpu_types.keys(),
 190                         default="atomic",
 191                         help="CPU model to use")
 192     parser.add_argument("--cpu-freq", type=str, default="4GHz")
 193     parser.add_argument("--num-cores", type=int, default=1,
 194                         help="Number of CPU cores")
 195     parser.add_argument("--mem-type", default="DDR3_1600_8x8",
 196                         choices=MemConfig.mem_names(),
 197                         help = "type of memory to use")
 198     parser.add_argument("--mem-channels", type=int, default=2,
 199                         help = "number of memory channels")
 200     parser.add_argument("--mem-ranks", type=int, default=None,
 201                         help = "number of memory ranks per channel")
 202     parser.add_argument("--mem-size", action="store", type=str,
 203                         default="2GB",
 204                         help="Specify the physical memory size")
 205
 206     args = parser.parse_args()
 207
 208     # Create a single root node for gem5's object hierarchy. There can
 209     # only exist one root node in the simulator at any given
 210     # time. Tell gem5 that we want to use syscall emulation mode
 211     # instead of full system mode.
 212     root = Root(full_system=False)
 213
 214     # Populate the root node with a system. A system corresponds to a
 215     # single node with shared memory.
 216     root.system = create(args)
 217
 218     # Instantiate the C++ object hierarchy. After this point,
 219     # SimObjects can't be instantiated anymore.
 220     m5.instantiate()
 221
 222     # Start the simulator. This gives control to the C++ world and
 223     # starts the simulator. The returned event tells the simulation
 224     # script why the simulator exited.
 225     event = m5.simulate()
 226
 227     # Print the reason for the simulation exit. Some exit codes are
 228     # requests for service (e.g., checkpoints) from the simulation
 229     # script. We'll just ignore them here and exit.
 230     print(event.getCause(), " @ ", m5.curTick())
 231     sys.exit(event.getCode())
 232
 233
 234 if __name__ == "__m5_main__":
 235     main()