configs/example/arm/starter_se.py

   1 # Copyright (c) 2016-2017 ARM Limited
   2 # All rights reserved.
   3 #
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  14 # modification, are permitted provided that the following conditions are
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  22 # this software without specific prior written permission.
  23 #
  24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35 #
  36 #  Authors:  Andreas Sandberg
  37 #            Chuan Zhu
  38 #            Gabor Dozsa
  39 #
  40
  41 """This script is the syscall emulation example script from the ARM
  42 Research Starter Kit on System Modeling. More information can be found
  43 at: http://www.arm.com/ResearchEnablement/SystemModeling
  44 """
  45
  46 import os
  47 import m5
  48 from m5.util import addToPath
  49 from m5.objects import *
  50 import argparse
  51 import shlex
  52
  53 m5.util.addToPath('../..')
  54
  55 from common import MemConfig
  56 from common.cores.arm import HPI
  57
  58 import devices
  59
  60
  61
  62 # Pre-defined CPU configurations. Each tuple must be ordered as : (cpu_class,
  63 # l1_icache_class, l1_dcache_class, walk_cache_class, l2_Cache_class). Any of
  64 # the cache class may be 'None' if the particular cache is not present.
  65 cpu_types = {
  66     "atomic" : ( AtomicSimpleCPU, None, None, None, None),
  67     "minor" : (MinorCPU,
  68                devices.L1I, devices.L1D,
  69                devices.WalkCache,
  70                devices.L2),
  71     "hpi" : ( HPI.HPI,
  72               HPI.HPI_ICache, HPI.HPI_DCache,
  73               HPI.HPI_WalkCache,
  74               HPI.HPI_L2)
  75 }
  76
  77
  78 class SimpleSeSystem(System):
  79     '''
  80     Example system class for syscall emulation mode
  81     '''
  82
  83     # Use a fixed cache line size of 64 bytes
  84     cache_line_size = 64
  85
  86     def __init__(self, args, **kwargs):
  87         super(SimpleSeSystem, self).__init__(**kwargs)
  88
  89         # Setup book keeping to be able to use CpuClusters from the
  90         # devices module.
  91         self._clusters = []
  92         self._num_cpus = 0
  93
  94         # Create a voltage and clock domain for system components
  95         self.voltage_domain = VoltageDomain(voltage="3.3V")
  96         self.clk_domain = SrcClockDomain(clock="1GHz",
  97                                          voltage_domain=self.voltage_domain)
  98
  99         # Create the off-chip memory bus.
 100         self.membus = SystemXBar()
 101
 102         # Wire up the system port that gem5 uses to load the kernel
 103         # and to perform debug accesses.
 104         self.system_port = self.membus.slave
 105
 106
 107         # Add CPUs to the system. A cluster of CPUs typically have
 108         # private L1 caches and a shared L2 cache.
 109         self.cpu_cluster = devices.CpuCluster(self,
 110                                               args.num_cores,
 111                                               args.cpu_freq, "1.2V",
 112                                               *cpu_types[args.cpu])
 113
 114         # Create a cache hierarchy (unless we are simulating a
 115         # functional CPU in atomic memory mode) for the CPU cluster
 116         # and connect it to the shared memory bus.
 117         if self.cpu_cluster.memoryMode() == "timing":
 118             self.cpu_cluster.addL1()
 119             self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
 120         self.cpu_cluster.connectMemSide(self.membus)
 121
 122         # Tell gem5 about the memory mode used by the CPUs we are
 123         # simulating.
 124         self.mem_mode = self.cpu_cluster.memoryMode()
 125
 126     def numCpuClusters(self):
 127         return len(self._clusters)
 128
 129     def addCpuCluster(self, cpu_cluster, num_cpus):
 130         assert cpu_cluster not in self._clusters
 131         assert num_cpus > 0
 132         self._clusters.append(cpu_cluster)
 133         self._num_cpus += num_cpus
 134
 135     def numCpus(self):
 136         return self._num_cpus
 137
 138 def get_processes(cmd):
 139     """Interprets commands to run and returns a list of processes"""
 140
 141     cwd = os.getcwd()
 142     multiprocesses = []
 143     for idx, c in enumerate(cmd):
 144         argv = shlex.split(c)
 145
 146         process = Process(pid=100 + idx, cwd=cwd, cmd=argv, executable=argv[0])
 147
 148         print "info: %d. command and arguments: %s" % (idx + 1, process.cmd)
 149         multiprocesses.append(process)
 150
 151     return multiprocesses
 152
 153
 154 def create(args):
 155     ''' Create and configure the system object. '''
 156
 157     system = SimpleSeSystem(args)
 158
 159     # Tell components about the expected physical memory ranges. This
 160     # is, for example, used by the MemConfig helper to determine where
 161     # to map DRAMs in the physical address space.
 162     system.mem_ranges = [ AddrRange(start=0, size=args.mem_size) ]
 163
 164     # Configure the off-chip memory system.
 165     MemConfig.config_mem(args, system)
 166
 167     # Parse the command line and get a list of Processes instances
 168     # that we can pass to gem5.
 169     processes = get_processes(args.commands_to_run)
 170     if len(processes) != args.num_cores:
 171         print "Error: Cannot map %d command(s) onto %d " \
 172             "CPU(s)" % (len(processes), args.num_cores)
 173         sys.exit(1)
 174
 175     # Assign one workload to each CPU
 176     for cpu, workload in zip(system.cpu_cluster.cpus, processes):
 177         cpu.workload = workload
 178
 179     return system
 180
 181
 182 def main():
 183     parser = argparse.ArgumentParser(epilog=__doc__)
 184
 185     parser.add_argument("commands_to_run", metavar="command(s)", nargs='*',
 186                         help="Command(s) to run")
 187     parser.add_argument("--cpu", type=str, choices=cpu_types.keys(),
 188                         default="atomic",
 189                         help="CPU model to use")
 190     parser.add_argument("--cpu-freq", type=str, default="4GHz")
 191     parser.add_argument("--num-cores", type=int, default=1,
 192                         help="Number of CPU cores")
 193     parser.add_argument("--mem-type", default="DDR3_1600_8x8",
 194                         choices=MemConfig.mem_names(),
 195                         help = "type of memory to use")
 196     parser.add_argument("--mem-channels", type=int, default=2,
 197                         help = "number of memory channels")
 198     parser.add_argument("--mem-ranks", type=int, default=None,
 199                         help = "number of memory ranks per channel")
 200     parser.add_argument("--mem-size", action="store", type=str,
 201                         default="2GB",
 202                         help="Specify the physical memory size")
 203
 204     args = parser.parse_args()
 205
 206     # Create a single root node for gem5's object hierarchy. There can
 207     # only exist one root node in the simulator at any given
 208     # time. Tell gem5 that we want to use syscall emulation mode
 209     # instead of full system mode.
 210     root = Root(full_system=False)
 211
 212     # Populate the root node with a system. A system corresponds to a
 213     # single node with shared memory.
 214     root.system = create(args)
 215
 216     # Instantiate the C++ object hierarchy. After this point,
 217     # SimObjects can't be instantiated anymore.
 218     m5.instantiate()
 219
 220     # Start the simulator. This gives control to the C++ world and
 221     # starts the simulator. The returned event tells the simulation
 222     # script why the simulator exited.
 223     event = m5.simulate()
 224
 225     # Print the reason for the simulation exit. Some exit codes are
 226     # requests for service (e.g., checkpoints) from the simulation
 227     # script. We'll just ignore them here and exit.
 228     print event.getCause(), " @ ", m5.curTick()
 229     sys.exit(event.getCode())
 230
 231
 232 if __name__ == "__m5_main__":
 233     main()