configs/example/etrace_replay.py

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  35
  36 # Basic elastic traces replay script that configures a Trace CPU
  37
  38 from __future__ import print_function
  39 from __future__ import absolute_import
  40
  41 import optparse
  42
  43 from m5.util import addToPath, fatal
  44
  45 addToPath('../')
  46
  47 from common import Options
  48 from common import Simulation
  49 from common import CacheConfig
  50 from common import MemConfig
  51 from common.Caches import *
  52
  53 parser = optparse.OptionParser()
  54 Options.addCommonOptions(parser)
  55
  56 if '--ruby' in sys.argv:
  57     print("This script does not support Ruby configuration, mainly"
  58     " because Trace CPU has been tested only with classic memory system")
  59     sys.exit(1)
  60
  61 (options, args) = parser.parse_args()
  62
  63 if args:
  64     print("Error: script doesn't take any positional arguments")
  65     sys.exit(1)
  66
  67 numThreads = 1
  68
  69 if options.cpu_type != "TraceCPU":
  70     fatal("This is a script for elastic trace replay simulation, use "\
  71             "--cpu-type=TraceCPU\n");
  72
  73 if options.num_cpus > 1:
  74     fatal("This script does not support multi-processor trace replay.\n")
  75
  76 # In this case FutureClass will be None as there is not fast forwarding or
  77 # switching
  78 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
  79 CPUClass.numThreads = numThreads
  80
  81 system = System(cpu = CPUClass(cpu_id=0),
  82                 mem_mode = test_mem_mode,
  83                 mem_ranges = [AddrRange(options.mem_size)],
  84                 cache_line_size = options.cacheline_size)
  85
  86 # Create a top-level voltage domain
  87 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
  88
  89 # Create a source clock for the system. This is used as the clock period for
  90 # xbar and memory
  91 system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
  92                                    voltage_domain = system.voltage_domain)
  93
  94 # Create a CPU voltage domain
  95 system.cpu_voltage_domain = VoltageDomain()
  96
  97 # Create a separate clock domain for the CPUs. In case of Trace CPUs this clock
  98 # is actually used only by the caches connected to the CPU.
  99 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 100                                        voltage_domain =
 101                                        system.cpu_voltage_domain)
 102
 103 # All cpus belong to a common cpu_clk_domain, therefore running at a common
 104 # frequency.
 105 for cpu in system.cpu:
 106     cpu.clk_domain = system.cpu_clk_domain
 107
 108 # BaseCPU no longer has default values for the BaseCPU.isa
 109 # createThreads() is needed to fill in the cpu.isa
 110 for cpu in system.cpu:
 111     cpu.createThreads()
 112
 113 # Assign input trace files to the Trace CPU
 114 system.cpu.instTraceFile=options.inst_trace_file
 115 system.cpu.dataTraceFile=options.data_trace_file
 116
 117 # Configure the classic memory system options
 118 MemClass = Simulation.setMemClass(options)
 119 system.membus = SystemXBar()
 120 system.system_port = system.membus.slave
 121 CacheConfig.config_cache(options, system)
 122 MemConfig.config_mem(options, system)
 123
 124 root = Root(full_system = False, system = system)
 125 Simulation.run(options, root, system, FutureClass)