configs/example/fs.py

   1 # Copyright (c) 2010-2013 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
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  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  14 # All rights reserved.
  15 #
  16 # Redistribution and use in source and binary forms, with or without
  17 # modification, are permitted provided that the following conditions are
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  23 # neither the name of the copyright holders nor the names of its
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  25 # this software without specific prior written permission.
  26 #
  27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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  37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38 #
  39 # Authors: Ali Saidi
  40
  41 import optparse
  42 import sys
  43
  44 import m5
  45 from m5.defines import buildEnv
  46 from m5.objects import *
  47 from m5.util import addToPath, fatal
  48
  49 addToPath('../common')
  50
  51 from FSConfig import *
  52 from SysPaths import *
  53 from Benchmarks import *
  54 import Simulation
  55 import CacheConfig
  56 import MemConfig
  57 from Caches import *
  58 import Options
  59
  60 parser = optparse.OptionParser()
  61 Options.addCommonOptions(parser)
  62 Options.addFSOptions(parser)
  63
  64 (options, args) = parser.parse_args()
  65
  66 if args:
  67     print "Error: script doesn't take any positional arguments"
  68     sys.exit(1)
  69
  70 # driver system CPU is always simple... note this is an assignment of
  71 # a class, not an instance.
  72 DriveCPUClass = AtomicSimpleCPU
  73 drive_mem_mode = 'atomic'
  74
  75 # Check if KVM support has been enabled, we might need to do VM
  76 # configuration if that's the case.
  77 have_kvm_support = 'BaseKvmCPU' in globals()
  78 def is_kvm_cpu(cpu_class):
  79     return have_kvm_support and cpu_class != None and \
  80         issubclass(cpu_class, BaseKvmCPU)
  81
  82 # system under test can be any CPU
  83 (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
  84
  85 # Match the memories with the CPUs, the driver system always simple,
  86 # and based on the options for the test system
  87 DriveMemClass = SimpleMemory
  88 TestMemClass = Simulation.setMemClass(options)
  89
  90 if options.benchmark:
  91     try:
  92         bm = Benchmarks[options.benchmark]
  93     except KeyError:
  94         print "Error benchmark %s has not been defined." % options.benchmark
  95         print "Valid benchmarks are: %s" % DefinedBenchmarks
  96         sys.exit(1)
  97 else:
  98     if options.dual:
  99         bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
 100     else:
 101         bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
 102
 103 np = options.num_cpus
 104
 105 if buildEnv['TARGET_ISA'] == "alpha":
 106     test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
 107 elif buildEnv['TARGET_ISA'] == "mips":
 108     test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
 109 elif buildEnv['TARGET_ISA'] == "sparc":
 110     test_sys = makeSparcSystem(test_mem_mode, bm[0])
 111 elif buildEnv['TARGET_ISA'] == "x86":
 112     test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
 113 elif buildEnv['TARGET_ISA'] == "arm":
 114     test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
 115                              options.dtb_filename,
 116                              bare_metal=options.bare_metal)
 117     if options.enable_context_switch_stats_dump:
 118         test_sys.enable_context_switch_stats_dump = True
 119 else:
 120     fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
 121
 122 # Create a top-level voltage domain
 123 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 124
 125 # Create a source clock for the system and set the clock period
 126 test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 127                                      voltage_domain = test_sys.voltage_domain)
 128
 129 # Create a CPU voltage domain
 130 test_sys.cpu_voltage_domain = VoltageDomain()
 131
 132 # Create a source clock for the CPUs and set the clock period
 133 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 134                                          voltage_domain =
 135                                          test_sys.cpu_voltage_domain)
 136
 137 if options.kernel is not None:
 138     test_sys.kernel = binary(options.kernel)
 139
 140 if options.script is not None:
 141     test_sys.readfile = options.script
 142
 143 test_sys.init_param = options.init_param
 144
 145 # For now, assign all the CPUs to the same clock domain
 146 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
 147                 for i in xrange(np)]
 148
 149 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
 150     test_sys.vm = KvmVM()
 151
 152 if options.caches or options.l2cache:
 153     # By default the IOCache runs at the system clock
 154     test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
 155     test_sys.iocache.cpu_side = test_sys.iobus.master
 156     test_sys.iocache.mem_side = test_sys.membus.slave
 157 else:
 158     test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
 159     test_sys.iobridge.slave = test_sys.iobus.master
 160     test_sys.iobridge.master = test_sys.membus.slave
 161
 162 # Sanity check
 163 if options.fastmem:
 164     if TestCPUClass != AtomicSimpleCPU:
 165         fatal("Fastmem can only be used with atomic CPU!")
 166     if (options.caches or options.l2cache):
 167         fatal("You cannot use fastmem in combination with caches!")
 168
 169 for i in xrange(np):
 170     if options.fastmem:
 171         test_sys.cpu[i].fastmem = True
 172     if options.checker:
 173         test_sys.cpu[i].addCheckerCpu()
 174     test_sys.cpu[i].createThreads()
 175
 176 CacheConfig.config_cache(options, test_sys)
 177 MemConfig.config_mem(options, test_sys)
 178
 179 if len(bm) == 2:
 180     if buildEnv['TARGET_ISA'] == 'alpha':
 181         drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
 182     elif buildEnv['TARGET_ISA'] == 'mips':
 183         drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
 184     elif buildEnv['TARGET_ISA'] == 'sparc':
 185         drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
 186     elif buildEnv['TARGET_ISA'] == 'x86':
 187         drive_sys = makeX86System(drive_mem_mode, np, bm[1])
 188     elif buildEnv['TARGET_ISA'] == 'arm':
 189         drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
 190
 191     # Create a top-level voltage domain
 192     drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 193
 194     # Create a source clock for the system and set the clock period
 195     drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock)
 196
 197     # Create a CPU voltage domain
 198     drive_sys.cpu_voltage_domain = VoltageDomain()
 199
 200     # Create a source clock for the CPUs and set the clock period
 201     drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 202                                               voltage_domain =
 203                                               drive_sys.cpu_voltage_domain)
 204
 205     drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
 206                                   cpu_id=0)
 207     drive_sys.cpu.createThreads()
 208     drive_sys.cpu.createInterruptController()
 209     drive_sys.cpu.connectAllPorts(drive_sys.membus)
 210     if options.fastmem:
 211         drive_sys.cpu.fastmem = True
 212     if options.kernel is not None:
 213         drive_sys.kernel = binary(options.kernel)
 214
 215     if is_kvm_cpu(DriveCPUClass):
 216         drive_sys.vm = KvmVM()
 217
 218     drive_sys.iobridge = Bridge(delay='50ns',
 219                                 ranges = drive_sys.mem_ranges)
 220     drive_sys.iobridge.slave = drive_sys.iobus.master
 221     drive_sys.iobridge.master = drive_sys.membus.slave
 222
 223     # Create the appropriate memory controllers and connect them to the
 224     # memory bus
 225     drive_sys.mem_ctrls = [DriveMemClass(range = r)
 226                            for r in drive_sys.mem_ranges]
 227     for i in xrange(len(drive_sys.mem_ctrls)):
 228         drive_sys.mem_ctrls[i].port = drive_sys.membus.master
 229
 230     drive_sys.init_param = options.init_param
 231     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 232 elif len(bm) == 1:
 233     root = Root(full_system=True, system=test_sys)
 234 else:
 235     print "Error I don't know how to create more than 2 systems."
 236     sys.exit(1)
 237
 238 if options.timesync:
 239     root.time_sync_enable = True
 240
 241 if options.frame_capture:
 242     VncServer.frame_capture = True
 243
 244 Simulation.setWorkCountOptions(test_sys, options)
 245 Simulation.run(options, root, test_sys, FutureClass)