configs/example/fs.py

   1 # Copyright (c) 2010-2013, 2016, 2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
  14 # Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
  15 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  16 # All rights reserved.
  17 #
  18 # Redistribution and use in source and binary forms, with or without
  19 # modification, are permitted provided that the following conditions are
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  23 # notice, this list of conditions and the following disclaimer in the
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  25 # neither the name of the copyright holders nor the names of its
  26 # contributors may be used to endorse or promote products derived from
  27 # this software without specific prior written permission.
  28 #
  29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40
  41 from __future__ import print_function
  42 from __future__ import absolute_import
  43
  44 import optparse
  45 import sys
  46
  47 import m5
  48 from m5.defines import buildEnv
  49 from m5.objects import *
  50 from m5.util import addToPath, fatal, warn
  51 from m5.util.fdthelper import *
  52
  53 addToPath('../')
  54
  55 from ruby import Ruby
  56
  57 from common.FSConfig import *
  58 from common.SysPaths import *
  59 from common.Benchmarks import *
  60 from common import Simulation
  61 from common import CacheConfig
  62 from common import CpuConfig
  63 from common import MemConfig
  64 from common import ObjectList
  65 from common.Caches import *
  66 from common import Options
  67
  68 def cmd_line_template():
  69     if options.command_line and options.command_line_file:
  70         print("Error: --command-line and --command-line-file are "
  71               "mutually exclusive")
  72         sys.exit(1)
  73     if options.command_line:
  74         return options.command_line
  75     if options.command_line_file:
  76         return open(options.command_line_file).read().strip()
  77     return None
  78
  79 def build_test_system(np):
  80     cmdline = cmd_line_template()
  81     if buildEnv['TARGET_ISA'] == "mips":
  82         test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
  83     elif buildEnv['TARGET_ISA'] == "sparc":
  84         test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
  85     elif buildEnv['TARGET_ISA'] == "x86":
  86         test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby,
  87                                       cmdline=cmdline)
  88     elif buildEnv['TARGET_ISA'] == "arm":
  89         test_sys = makeArmSystem(
  90             test_mem_mode,
  91             options.machine_type,
  92             np,
  93             bm[0],
  94             options.dtb_filename,
  95             bare_metal=options.bare_metal,
  96             cmdline=cmdline,
  97             external_memory=options.external_memory_system,
  98             ruby=options.ruby,
  99             security=options.enable_security_extensions,
 100             vio_9p=options.vio_9p,
 101             bootloader=options.bootloader,
 102         )
 103         if options.enable_context_switch_stats_dump:
 104             test_sys.enable_context_switch_stats_dump = True
 105     else:
 106         fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
 107
 108     # Set the cache line size for the entire system
 109     test_sys.cache_line_size = options.cacheline_size
 110
 111     # Create a top-level voltage domain
 112     test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 113
 114     # Create a source clock for the system and set the clock period
 115     test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 116             voltage_domain = test_sys.voltage_domain)
 117
 118     # Create a CPU voltage domain
 119     test_sys.cpu_voltage_domain = VoltageDomain()
 120
 121     # Create a source clock for the CPUs and set the clock period
 122     test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 123                                              voltage_domain =
 124                                              test_sys.cpu_voltage_domain)
 125
 126     if options.kernel is not None:
 127         test_sys.workload.object_file = binary(options.kernel)
 128
 129     if options.script is not None:
 130         test_sys.readfile = options.script
 131
 132     if options.lpae:
 133         test_sys.have_lpae = True
 134
 135     if options.virtualisation:
 136         test_sys.have_virtualization = True
 137
 138     test_sys.init_param = options.init_param
 139
 140     # For now, assign all the CPUs to the same clock domain
 141     test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
 142                     for i in range(np)]
 143
 144     if ObjectList.is_kvm_cpu(TestCPUClass) or \
 145         ObjectList.is_kvm_cpu(FutureClass):
 146         test_sys.kvm_vm = KvmVM()
 147
 148     if options.ruby:
 149         bootmem = getattr(test_sys, '_bootmem', None)
 150         Ruby.create_system(options, True, test_sys, test_sys.iobus,
 151                            test_sys._dma_ports, bootmem)
 152
 153         # Create a seperate clock domain for Ruby
 154         test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
 155                                         voltage_domain = test_sys.voltage_domain)
 156
 157         # Connect the ruby io port to the PIO bus,
 158         # assuming that there is just one such port.
 159         test_sys.iobus.master = test_sys.ruby._io_port.slave
 160
 161         for (i, cpu) in enumerate(test_sys.cpu):
 162             #
 163             # Tie the cpu ports to the correct ruby system ports
 164             #
 165             cpu.clk_domain = test_sys.cpu_clk_domain
 166             cpu.createThreads()
 167             cpu.createInterruptController()
 168
 169             cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
 170             cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
 171
 172             if buildEnv['TARGET_ISA'] in ("x86", "arm"):
 173                 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
 174                 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
 175
 176             if buildEnv['TARGET_ISA'] in "x86":
 177                 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
 178                 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
 179                 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
 180
 181     else:
 182         if options.caches or options.l2cache:
 183             # By default the IOCache runs at the system clock
 184             test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
 185             test_sys.iocache.cpu_side = test_sys.iobus.master
 186             test_sys.iocache.mem_side = test_sys.membus.slave
 187         elif not options.external_memory_system:
 188             test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
 189             test_sys.iobridge.slave = test_sys.iobus.master
 190             test_sys.iobridge.master = test_sys.membus.slave
 191
 192         # Sanity check
 193         if options.simpoint_profile:
 194             if not ObjectList.is_noncaching_cpu(TestCPUClass):
 195                 fatal("SimPoint generation should be done with atomic cpu")
 196             if np > 1:
 197                 fatal("SimPoint generation not supported with more than one CPUs")
 198
 199         for i in range(np):
 200             if options.simpoint_profile:
 201                 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
 202             if options.checker:
 203                 test_sys.cpu[i].addCheckerCpu()
 204             if not ObjectList.is_kvm_cpu(TestCPUClass):
 205                 if options.bp_type:
 206                     bpClass = ObjectList.bp_list.get(options.bp_type)
 207                     test_sys.cpu[i].branchPred = bpClass()
 208                 if options.indirect_bp_type:
 209                     IndirectBPClass = ObjectList.indirect_bp_list.get(
 210                         options.indirect_bp_type)
 211                     test_sys.cpu[i].branchPred.indirectBranchPred = \
 212                         IndirectBPClass()
 213             test_sys.cpu[i].createThreads()
 214
 215         # If elastic tracing is enabled when not restoring from checkpoint and
 216         # when not fast forwarding using the atomic cpu, then check that the
 217         # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
 218         # passes then attach the elastic trace probe.
 219         # If restoring from checkpoint or fast forwarding, the code that does this for
 220         # FutureCPUClass is in the Simulation module. If the check passes then the
 221         # elastic trace probe is attached to the switch CPUs.
 222         if options.elastic_trace_en and options.checkpoint_restore == None and \
 223             not options.fast_forward:
 224             CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
 225
 226         CacheConfig.config_cache(options, test_sys)
 227
 228         MemConfig.config_mem(options, test_sys)
 229
 230     return test_sys
 231
 232 def build_drive_system(np):
 233     # driver system CPU is always simple, so is the memory
 234     # Note this is an assignment of a class, not an instance.
 235     DriveCPUClass = AtomicSimpleCPU
 236     drive_mem_mode = 'atomic'
 237     DriveMemClass = SimpleMemory
 238
 239     cmdline = cmd_line_template()
 240     if buildEnv['TARGET_ISA'] == 'mips':
 241         drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
 242     elif buildEnv['TARGET_ISA'] == 'sparc':
 243         drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
 244     elif buildEnv['TARGET_ISA'] == 'x86':
 245         drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
 246                                        cmdline=cmdline)
 247     elif buildEnv['TARGET_ISA'] == 'arm':
 248         drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
 249                                   bm[1], options.dtb_filename, cmdline=cmdline)
 250
 251     # Create a top-level voltage domain
 252     drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 253
 254     # Create a source clock for the system and set the clock period
 255     drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 256             voltage_domain = drive_sys.voltage_domain)
 257
 258     # Create a CPU voltage domain
 259     drive_sys.cpu_voltage_domain = VoltageDomain()
 260
 261     # Create a source clock for the CPUs and set the clock period
 262     drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 263                                               voltage_domain =
 264                                               drive_sys.cpu_voltage_domain)
 265
 266     drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
 267                                   cpu_id=0)
 268     drive_sys.cpu.createThreads()
 269     drive_sys.cpu.createInterruptController()
 270     drive_sys.cpu.connectAllPorts(drive_sys.membus)
 271     if options.kernel is not None:
 272         drive_sys.workload.object_file = binary(options.kernel)
 273
 274     if ObjectList.is_kvm_cpu(DriveCPUClass):
 275         drive_sys.kvm_vm = KvmVM()
 276
 277     drive_sys.iobridge = Bridge(delay='50ns',
 278                                 ranges = drive_sys.mem_ranges)
 279     drive_sys.iobridge.slave = drive_sys.iobus.master
 280     drive_sys.iobridge.master = drive_sys.membus.slave
 281
 282     # Create the appropriate memory controllers and connect them to the
 283     # memory bus
 284     drive_sys.mem_ctrls = [DriveMemClass(range = r)
 285                            for r in drive_sys.mem_ranges]
 286     for i in range(len(drive_sys.mem_ctrls)):
 287         drive_sys.mem_ctrls[i].port = drive_sys.membus.master
 288
 289     drive_sys.init_param = options.init_param
 290
 291     return drive_sys
 292
 293 # Add options
 294 parser = optparse.OptionParser()
 295 Options.addCommonOptions(parser)
 296 Options.addFSOptions(parser)
 297
 298 # Add the ruby specific and protocol specific options
 299 if '--ruby' in sys.argv:
 300     Ruby.define_options(parser)
 301
 302 (options, args) = parser.parse_args()
 303
 304 if args:
 305     print("Error: script doesn't take any positional arguments")
 306     sys.exit(1)
 307
 308 # system under test can be any CPU
 309 (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 310
 311 # Match the memories with the CPUs, based on the options for the test system
 312 TestMemClass = Simulation.setMemClass(options)
 313
 314 if options.benchmark:
 315     try:
 316         bm = Benchmarks[options.benchmark]
 317     except KeyError:
 318         print("Error benchmark %s has not been defined." % options.benchmark)
 319         print("Valid benchmarks are: %s" % DefinedBenchmarks)
 320         sys.exit(1)
 321 else:
 322     if options.dual:
 323         bm = [SysConfig(disks=options.disk_image, rootdev=options.root_device,
 324                         mem=options.mem_size, os_type=options.os_type),
 325               SysConfig(disks=options.disk_image, rootdev=options.root_device,
 326                         mem=options.mem_size, os_type=options.os_type)]
 327     else:
 328         bm = [SysConfig(disks=options.disk_image, rootdev=options.root_device,
 329                         mem=options.mem_size, os_type=options.os_type)]
 330
 331 np = options.num_cpus
 332
 333 test_sys = build_test_system(np)
 334 if len(bm) == 2:
 335     drive_sys = build_drive_system(np)
 336     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 337 elif len(bm) == 1 and options.dist:
 338     # This system is part of a dist-gem5 simulation
 339     root = makeDistRoot(test_sys,
 340                         options.dist_rank,
 341                         options.dist_size,
 342                         options.dist_server_name,
 343                         options.dist_server_port,
 344                         options.dist_sync_repeat,
 345                         options.dist_sync_start,
 346                         options.ethernet_linkspeed,
 347                         options.ethernet_linkdelay,
 348                         options.etherdump);
 349 elif len(bm) == 1:
 350     root = Root(full_system=True, system=test_sys)
 351 else:
 352     print("Error I don't know how to create more than 2 systems.")
 353     sys.exit(1)
 354
 355 if options.timesync:
 356     root.time_sync_enable = True
 357
 358 if options.frame_capture:
 359     VncServer.frame_capture = True
 360
 361 if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \
 362         and not options.dtb_filename:
 363     if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
 364         warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
 365              "platforms, unless custom hardware models have been equipped "\
 366              "with generation functionality.")
 367
 368     # Generate a Device Tree
 369     for sysname in ('system', 'testsys', 'drivesys'):
 370         if hasattr(root, sysname):
 371             sys = getattr(root, sysname)
 372             sys.workload.dtb_filename = \
 373                 os.path.join(m5.options.outdir, '%s.dtb' % sysname)
 374             sys.generateDtb(sys.workload.dtb_filename)
 375
 376 Simulation.setWorkCountOptions(test_sys, options)
 377 Simulation.run(options, root, test_sys, FutureClass)