configs/example/fs.py

   1 # Copyright (c) 2010-2013, 2016, 2019 ARM Limited
   2 # Copyright (c) 2020 Barkhausen Institut
   3 # All rights reserved.
   4 #
   5 # The license below extends only to copyright in the software and shall
   6 # not be construed as granting a license to any other intellectual
   7 # property including but not limited to intellectual property relating
   8 # to a hardware implementation of the functionality of the software
   9 # licensed hereunder.  You may use the software subject to the license
  10 # terms below provided that you ensure that this notice is replicated
  11 # unmodified and in its entirety in all distributions of the software,
  12 # modified or unmodified, in source code or in binary form.
  13 #
  14 # Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
  15 # Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
  16 # Copyright (c) 2006-2007 The Regents of The University of Michigan
  17 # All rights reserved.
  18 #
  19 # Redistribution and use in source and binary forms, with or without
  20 # modification, are permitted provided that the following conditions are
  21 # met: redistributions of source code must retain the above copyright
  22 # notice, this list of conditions and the following disclaimer;
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  24 # notice, this list of conditions and the following disclaimer in the
  25 # documentation and/or other materials provided with the distribution;
  26 # neither the name of the copyright holders nor the names of its
  27 # contributors may be used to endorse or promote products derived from
  28 # this software without specific prior written permission.
  29 #
  30 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  31 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  32 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  33 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  34 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  40 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  41
  42 from __future__ import print_function
  43 from __future__ import absolute_import
  44
  45 import optparse
  46 import sys
  47
  48 import m5
  49 from m5.defines import buildEnv
  50 from m5.objects import *
  51 from m5.util import addToPath, fatal, warn
  52 from m5.util.fdthelper import *
  53
  54 addToPath('../')
  55
  56 from ruby import Ruby
  57
  58 from common.FSConfig import *
  59 from common.SysPaths import *
  60 from common.Benchmarks import *
  61 from common import Simulation
  62 from common import CacheConfig
  63 from common import CpuConfig
  64 from common import MemConfig
  65 from common import ObjectList
  66 from common.Caches import *
  67 from common import Options
  68
  69 def cmd_line_template():
  70     if options.command_line and options.command_line_file:
  71         print("Error: --command-line and --command-line-file are "
  72               "mutually exclusive")
  73         sys.exit(1)
  74     if options.command_line:
  75         return options.command_line
  76     if options.command_line_file:
  77         return open(options.command_line_file).read().strip()
  78     return None
  79
  80 def build_test_system(np):
  81     cmdline = cmd_line_template()
  82     if buildEnv['TARGET_ISA'] == "mips":
  83         test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
  84     elif buildEnv['TARGET_ISA'] == "sparc":
  85         test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
  86     elif buildEnv['TARGET_ISA'] == "riscv":
  87         test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0],
  88                                             cmdline=cmdline)
  89     elif buildEnv['TARGET_ISA'] == "x86":
  90         test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby,
  91                                       cmdline=cmdline)
  92     elif buildEnv['TARGET_ISA'] == "arm":
  93         test_sys = makeArmSystem(
  94             test_mem_mode,
  95             options.machine_type,
  96             np,
  97             bm[0],
  98             options.dtb_filename,
  99             bare_metal=options.bare_metal,
 100             cmdline=cmdline,
 101             external_memory=options.external_memory_system,
 102             ruby=options.ruby,
 103             security=options.enable_security_extensions,
 104             vio_9p=options.vio_9p,
 105             bootloader=options.bootloader,
 106         )
 107         if options.enable_context_switch_stats_dump:
 108             test_sys.enable_context_switch_stats_dump = True
 109     else:
 110         fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
 111
 112     # Set the cache line size for the entire system
 113     test_sys.cache_line_size = options.cacheline_size
 114
 115     # Create a top-level voltage domain
 116     test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 117
 118     # Create a source clock for the system and set the clock period
 119     test_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 120             voltage_domain = test_sys.voltage_domain)
 121
 122     # Create a CPU voltage domain
 123     test_sys.cpu_voltage_domain = VoltageDomain()
 124
 125     # Create a source clock for the CPUs and set the clock period
 126     test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 127                                              voltage_domain =
 128                                              test_sys.cpu_voltage_domain)
 129
 130     if buildEnv['TARGET_ISA'] == 'riscv':
 131         test_sys.workload.bootloader = options.kernel
 132     elif options.kernel is not None:
 133         test_sys.workload.object_file = binary(options.kernel)
 134
 135     if options.script is not None:
 136         test_sys.readfile = options.script
 137
 138     if options.lpae:
 139         test_sys.have_lpae = True
 140
 141     if options.virtualisation:
 142         test_sys.have_virtualization = True
 143
 144     test_sys.init_param = options.init_param
 145
 146     # For now, assign all the CPUs to the same clock domain
 147     test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
 148                     for i in range(np)]
 149
 150     if ObjectList.is_kvm_cpu(TestCPUClass) or \
 151         ObjectList.is_kvm_cpu(FutureClass):
 152         test_sys.kvm_vm = KvmVM()
 153
 154     if options.ruby:
 155         bootmem = getattr(test_sys, '_bootmem', None)
 156         Ruby.create_system(options, True, test_sys, test_sys.iobus,
 157                            test_sys._dma_ports, bootmem)
 158
 159         # Create a seperate clock domain for Ruby
 160         test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
 161                                         voltage_domain = test_sys.voltage_domain)
 162
 163         # Connect the ruby io port to the PIO bus,
 164         # assuming that there is just one such port.
 165         test_sys.iobus.master = test_sys.ruby._io_port.slave
 166
 167         for (i, cpu) in enumerate(test_sys.cpu):
 168             #
 169             # Tie the cpu ports to the correct ruby system ports
 170             #
 171             cpu.clk_domain = test_sys.cpu_clk_domain
 172             cpu.createThreads()
 173             cpu.createInterruptController()
 174
 175             cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
 176             cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
 177
 178             if buildEnv['TARGET_ISA'] in ("x86", "arm"):
 179                 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
 180                 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
 181
 182             if buildEnv['TARGET_ISA'] in "x86":
 183                 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
 184                 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
 185                 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
 186
 187     else:
 188         if options.caches or options.l2cache:
 189             # By default the IOCache runs at the system clock
 190             test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
 191             test_sys.iocache.cpu_side = test_sys.iobus.master
 192             test_sys.iocache.mem_side = test_sys.membus.slave
 193         elif not options.external_memory_system:
 194             test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
 195             test_sys.iobridge.slave = test_sys.iobus.master
 196             test_sys.iobridge.master = test_sys.membus.slave
 197
 198         # Sanity check
 199         if options.simpoint_profile:
 200             if not ObjectList.is_noncaching_cpu(TestCPUClass):
 201                 fatal("SimPoint generation should be done with atomic cpu")
 202             if np > 1:
 203                 fatal("SimPoint generation not supported with more than one CPUs")
 204
 205         for i in range(np):
 206             if options.simpoint_profile:
 207                 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
 208             if options.checker:
 209                 test_sys.cpu[i].addCheckerCpu()
 210             if not ObjectList.is_kvm_cpu(TestCPUClass):
 211                 if options.bp_type:
 212                     bpClass = ObjectList.bp_list.get(options.bp_type)
 213                     test_sys.cpu[i].branchPred = bpClass()
 214                 if options.indirect_bp_type:
 215                     IndirectBPClass = ObjectList.indirect_bp_list.get(
 216                         options.indirect_bp_type)
 217                     test_sys.cpu[i].branchPred.indirectBranchPred = \
 218                         IndirectBPClass()
 219             test_sys.cpu[i].createThreads()
 220
 221         # If elastic tracing is enabled when not restoring from checkpoint and
 222         # when not fast forwarding using the atomic cpu, then check that the
 223         # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
 224         # passes then attach the elastic trace probe.
 225         # If restoring from checkpoint or fast forwarding, the code that does this for
 226         # FutureCPUClass is in the Simulation module. If the check passes then the
 227         # elastic trace probe is attached to the switch CPUs.
 228         if options.elastic_trace_en and options.checkpoint_restore == None and \
 229             not options.fast_forward:
 230             CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
 231
 232         CacheConfig.config_cache(options, test_sys)
 233
 234         MemConfig.config_mem(options, test_sys)
 235
 236     return test_sys
 237
 238 def build_drive_system(np):
 239     # driver system CPU is always simple, so is the memory
 240     # Note this is an assignment of a class, not an instance.
 241     DriveCPUClass = AtomicSimpleCPU
 242     drive_mem_mode = 'atomic'
 243     DriveMemClass = SimpleMemory
 244
 245     cmdline = cmd_line_template()
 246     if buildEnv['TARGET_ISA'] == 'mips':
 247         drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
 248     elif buildEnv['TARGET_ISA'] == 'sparc':
 249         drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
 250     elif buildEnv['TARGET_ISA'] == 'x86':
 251         drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
 252                                        cmdline=cmdline)
 253     elif buildEnv['TARGET_ISA'] == 'arm':
 254         drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
 255                                   bm[1], options.dtb_filename, cmdline=cmdline)
 256
 257     # Create a top-level voltage domain
 258     drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
 259
 260     # Create a source clock for the system and set the clock period
 261     drive_sys.clk_domain = SrcClockDomain(clock =  options.sys_clock,
 262             voltage_domain = drive_sys.voltage_domain)
 263
 264     # Create a CPU voltage domain
 265     drive_sys.cpu_voltage_domain = VoltageDomain()
 266
 267     # Create a source clock for the CPUs and set the clock period
 268     drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
 269                                               voltage_domain =
 270                                               drive_sys.cpu_voltage_domain)
 271
 272     drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
 273                                   cpu_id=0)
 274     drive_sys.cpu.createThreads()
 275     drive_sys.cpu.createInterruptController()
 276     drive_sys.cpu.connectAllPorts(drive_sys.membus)
 277     if options.kernel is not None:
 278         drive_sys.workload.object_file = binary(options.kernel)
 279
 280     if ObjectList.is_kvm_cpu(DriveCPUClass):
 281         drive_sys.kvm_vm = KvmVM()
 282
 283     drive_sys.iobridge = Bridge(delay='50ns',
 284                                 ranges = drive_sys.mem_ranges)
 285     drive_sys.iobridge.slave = drive_sys.iobus.master
 286     drive_sys.iobridge.master = drive_sys.membus.slave
 287
 288     # Create the appropriate memory controllers and connect them to the
 289     # memory bus
 290     drive_sys.mem_ctrls = [DriveMemClass(range = r)
 291                            for r in drive_sys.mem_ranges]
 292     for i in range(len(drive_sys.mem_ctrls)):
 293         drive_sys.mem_ctrls[i].port = drive_sys.membus.master
 294
 295     drive_sys.init_param = options.init_param
 296
 297     return drive_sys
 298
 299 # Add options
 300 parser = optparse.OptionParser()
 301 Options.addCommonOptions(parser)
 302 Options.addFSOptions(parser)
 303
 304 # Add the ruby specific and protocol specific options
 305 if '--ruby' in sys.argv:
 306     Ruby.define_options(parser)
 307
 308 (options, args) = parser.parse_args()
 309
 310 if args:
 311     print("Error: script doesn't take any positional arguments")
 312     sys.exit(1)
 313
 314 # system under test can be any CPU
 315 (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 316
 317 # Match the memories with the CPUs, based on the options for the test system
 318 TestMemClass = Simulation.setMemClass(options)
 319
 320 if options.benchmark:
 321     try:
 322         bm = Benchmarks[options.benchmark]
 323     except KeyError:
 324         print("Error benchmark %s has not been defined." % options.benchmark)
 325         print("Valid benchmarks are: %s" % DefinedBenchmarks)
 326         sys.exit(1)
 327 else:
 328     if options.dual:
 329         bm = [SysConfig(disks=options.disk_image, rootdev=options.root_device,
 330                         mem=options.mem_size, os_type=options.os_type),
 331               SysConfig(disks=options.disk_image, rootdev=options.root_device,
 332                         mem=options.mem_size, os_type=options.os_type)]
 333     else:
 334         bm = [SysConfig(disks=options.disk_image, rootdev=options.root_device,
 335                         mem=options.mem_size, os_type=options.os_type)]
 336
 337 np = options.num_cpus
 338
 339 test_sys = build_test_system(np)
 340 if len(bm) == 2:
 341     drive_sys = build_drive_system(np)
 342     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 343 elif len(bm) == 1 and options.dist:
 344     # This system is part of a dist-gem5 simulation
 345     root = makeDistRoot(test_sys,
 346                         options.dist_rank,
 347                         options.dist_size,
 348                         options.dist_server_name,
 349                         options.dist_server_port,
 350                         options.dist_sync_repeat,
 351                         options.dist_sync_start,
 352                         options.ethernet_linkspeed,
 353                         options.ethernet_linkdelay,
 354                         options.etherdump);
 355 elif len(bm) == 1:
 356     root = Root(full_system=True, system=test_sys)
 357 else:
 358     print("Error I don't know how to create more than 2 systems.")
 359     sys.exit(1)
 360
 361 if options.timesync:
 362     root.time_sync_enable = True
 363
 364 if options.frame_capture:
 365     VncServer.frame_capture = True
 366
 367 if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \
 368         and not options.dtb_filename:
 369     if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
 370         warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
 371              "platforms, unless custom hardware models have been equipped "\
 372              "with generation functionality.")
 373
 374     # Generate a Device Tree
 375     for sysname in ('system', 'testsys', 'drivesys'):
 376         if hasattr(root, sysname):
 377             sys = getattr(root, sysname)
 378             sys.workload.dtb_filename = \
 379                 os.path.join(m5.options.outdir, '%s.dtb' % sysname)
 380             sys.generateDtb(sys.workload.dtb_filename)
 381
 382 Simulation.setWorkCountOptions(test_sys, options)
 383 Simulation.run(options, root, test_sys, FutureClass)