1 # Copyright (c) 2010-2013, 2016, 2019 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14 # Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15 # Copyright (c) 2006-2007 The Regents of The University of Michigan
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 from __future__
import print_function
50 from m5
.defines
import buildEnv
51 from m5
.objects
import *
52 from m5
.util
import addToPath
, fatal
, warn
53 from m5
.util
.fdthelper
import *
59 from common
.FSConfig
import *
60 from common
.SysPaths
import *
61 from common
.Benchmarks
import *
62 from common
import Simulation
63 from common
import CacheConfig
64 from common
import MemConfig
65 from common
import CpuConfig
66 from common
import BPConfig
67 from common
.Caches
import *
68 from common
import Options
70 def cmd_line_template():
71 if options
.command_line
and options
.command_line_file
:
72 print("Error: --command-line and --command-line-file are "
75 if options
.command_line
:
76 return options
.command_line
77 if options
.command_line_file
:
78 return open(options
.command_line_file
).read().strip()
81 def build_test_system(np
):
82 cmdline
= cmd_line_template()
83 if buildEnv
['TARGET_ISA'] == "alpha":
84 test_sys
= makeLinuxAlphaSystem(test_mem_mode
, bm
[0], options
.ruby
,
86 elif buildEnv
['TARGET_ISA'] == "mips":
87 test_sys
= makeLinuxMipsSystem(test_mem_mode
, bm
[0], cmdline
=cmdline
)
88 elif buildEnv
['TARGET_ISA'] == "sparc":
89 test_sys
= makeSparcSystem(test_mem_mode
, bm
[0], cmdline
=cmdline
)
90 elif buildEnv
['TARGET_ISA'] == "x86":
91 test_sys
= makeLinuxX86System(test_mem_mode
, options
.num_cpus
, bm
[0],
92 options
.ruby
, cmdline
=cmdline
)
93 elif buildEnv
['TARGET_ISA'] == "arm":
94 test_sys
= makeArmSystem(test_mem_mode
, options
.machine_type
,
95 options
.num_cpus
, bm
[0], options
.dtb_filename
,
96 bare_metal
=options
.bare_metal
,
99 options
.external_memory_system
,
101 security
=options
.enable_security_extensions
)
102 if options
.enable_context_switch_stats_dump
:
103 test_sys
.enable_context_switch_stats_dump
= True
105 fatal("Incapable of building %s full system!", buildEnv
['TARGET_ISA'])
107 # Set the cache line size for the entire system
108 test_sys
.cache_line_size
= options
.cacheline_size
110 # Create a top-level voltage domain
111 test_sys
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
113 # Create a source clock for the system and set the clock period
114 test_sys
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
115 voltage_domain
= test_sys
.voltage_domain
)
117 # Create a CPU voltage domain
118 test_sys
.cpu_voltage_domain
= VoltageDomain()
120 # Create a source clock for the CPUs and set the clock period
121 test_sys
.cpu_clk_domain
= SrcClockDomain(clock
= options
.cpu_clock
,
123 test_sys
.cpu_voltage_domain
)
125 if options
.kernel
is not None:
126 test_sys
.kernel
= binary(options
.kernel
)
128 if options
.script
is not None:
129 test_sys
.readfile
= options
.script
132 test_sys
.have_lpae
= True
134 if options
.virtualisation
:
135 test_sys
.have_virtualization
= True
137 test_sys
.init_param
= options
.init_param
139 # For now, assign all the CPUs to the same clock domain
140 test_sys
.cpu
= [TestCPUClass(clk_domain
=test_sys
.cpu_clk_domain
, cpu_id
=i
)
143 if CpuConfig
.is_kvm_cpu(TestCPUClass
) or CpuConfig
.is_kvm_cpu(FutureClass
):
144 test_sys
.kvm_vm
= KvmVM()
147 bootmem
= getattr(test_sys
, 'bootmem', None)
148 Ruby
.create_system(options
, True, test_sys
, test_sys
.iobus
,
149 test_sys
._dma
_ports
, bootmem
)
151 # Create a seperate clock domain for Ruby
152 test_sys
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
,
153 voltage_domain
= test_sys
.voltage_domain
)
155 # Connect the ruby io port to the PIO bus,
156 # assuming that there is just one such port.
157 test_sys
.iobus
.master
= test_sys
.ruby
._io
_port
.slave
159 for (i
, cpu
) in enumerate(test_sys
.cpu
):
161 # Tie the cpu ports to the correct ruby system ports
163 cpu
.clk_domain
= test_sys
.cpu_clk_domain
165 cpu
.createInterruptController()
167 cpu
.icache_port
= test_sys
.ruby
._cpu
_ports
[i
].slave
168 cpu
.dcache_port
= test_sys
.ruby
._cpu
_ports
[i
].slave
170 if buildEnv
['TARGET_ISA'] in ("x86", "arm"):
171 cpu
.itb
.walker
.port
= test_sys
.ruby
._cpu
_ports
[i
].slave
172 cpu
.dtb
.walker
.port
= test_sys
.ruby
._cpu
_ports
[i
].slave
174 if buildEnv
['TARGET_ISA'] in "x86":
175 cpu
.interrupts
[0].pio
= test_sys
.ruby
._cpu
_ports
[i
].master
176 cpu
.interrupts
[0].int_master
= test_sys
.ruby
._cpu
_ports
[i
].slave
177 cpu
.interrupts
[0].int_slave
= test_sys
.ruby
._cpu
_ports
[i
].master
180 if options
.caches
or options
.l2cache
:
181 # By default the IOCache runs at the system clock
182 test_sys
.iocache
= IOCache(addr_ranges
= test_sys
.mem_ranges
)
183 test_sys
.iocache
.cpu_side
= test_sys
.iobus
.master
184 test_sys
.iocache
.mem_side
= test_sys
.membus
.slave
185 elif not options
.external_memory_system
:
186 test_sys
.iobridge
= Bridge(delay
='50ns', ranges
= test_sys
.mem_ranges
)
187 test_sys
.iobridge
.slave
= test_sys
.iobus
.master
188 test_sys
.iobridge
.master
= test_sys
.membus
.slave
191 if options
.simpoint_profile
:
192 if not CpuConfig
.is_noncaching_cpu(TestCPUClass
):
193 fatal("SimPoint generation should be done with atomic cpu")
195 fatal("SimPoint generation not supported with more than one CPUs")
198 if options
.simpoint_profile
:
199 test_sys
.cpu
[i
].addSimPointProbe(options
.simpoint_interval
)
201 test_sys
.cpu
[i
].addCheckerCpu()
203 bpClass
= BPConfig
.get(options
.bp_type
)
204 test_sys
.cpu
[i
].branchPred
= bpClass()
205 test_sys
.cpu
[i
].createThreads()
207 # If elastic tracing is enabled when not restoring from checkpoint and
208 # when not fast forwarding using the atomic cpu, then check that the
209 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
210 # passes then attach the elastic trace probe.
211 # If restoring from checkpoint or fast forwarding, the code that does this for
212 # FutureCPUClass is in the Simulation module. If the check passes then the
213 # elastic trace probe is attached to the switch CPUs.
214 if options
.elastic_trace_en
and options
.checkpoint_restore
== None and \
215 not options
.fast_forward
:
216 CpuConfig
.config_etrace(TestCPUClass
, test_sys
.cpu
, options
)
218 CacheConfig
.config_cache(options
, test_sys
)
220 MemConfig
.config_mem(options
, test_sys
)
224 def build_drive_system(np
):
225 # driver system CPU is always simple, so is the memory
226 # Note this is an assignment of a class, not an instance.
227 DriveCPUClass
= AtomicSimpleCPU
228 drive_mem_mode
= 'atomic'
229 DriveMemClass
= SimpleMemory
231 cmdline
= cmd_line_template()
232 if buildEnv
['TARGET_ISA'] == 'alpha':
233 drive_sys
= makeLinuxAlphaSystem(drive_mem_mode
, bm
[1], cmdline
=cmdline
)
234 elif buildEnv
['TARGET_ISA'] == 'mips':
235 drive_sys
= makeLinuxMipsSystem(drive_mem_mode
, bm
[1], cmdline
=cmdline
)
236 elif buildEnv
['TARGET_ISA'] == 'sparc':
237 drive_sys
= makeSparcSystem(drive_mem_mode
, bm
[1], cmdline
=cmdline
)
238 elif buildEnv
['TARGET_ISA'] == 'x86':
239 drive_sys
= makeLinuxX86System(drive_mem_mode
, np
, bm
[1],
241 elif buildEnv
['TARGET_ISA'] == 'arm':
242 drive_sys
= makeArmSystem(drive_mem_mode
, options
.machine_type
, np
,
243 bm
[1], options
.dtb_filename
, cmdline
=cmdline
)
245 # Create a top-level voltage domain
246 drive_sys
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
248 # Create a source clock for the system and set the clock period
249 drive_sys
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
250 voltage_domain
= drive_sys
.voltage_domain
)
252 # Create a CPU voltage domain
253 drive_sys
.cpu_voltage_domain
= VoltageDomain()
255 # Create a source clock for the CPUs and set the clock period
256 drive_sys
.cpu_clk_domain
= SrcClockDomain(clock
= options
.cpu_clock
,
258 drive_sys
.cpu_voltage_domain
)
260 drive_sys
.cpu
= DriveCPUClass(clk_domain
=drive_sys
.cpu_clk_domain
,
262 drive_sys
.cpu
.createThreads()
263 drive_sys
.cpu
.createInterruptController()
264 drive_sys
.cpu
.connectAllPorts(drive_sys
.membus
)
265 if options
.kernel
is not None:
266 drive_sys
.kernel
= binary(options
.kernel
)
268 if CpuConfig
.is_kvm_cpu(DriveCPUClass
):
269 drive_sys
.kvm_vm
= KvmVM()
271 drive_sys
.iobridge
= Bridge(delay
='50ns',
272 ranges
= drive_sys
.mem_ranges
)
273 drive_sys
.iobridge
.slave
= drive_sys
.iobus
.master
274 drive_sys
.iobridge
.master
= drive_sys
.membus
.slave
276 # Create the appropriate memory controllers and connect them to the
278 drive_sys
.mem_ctrls
= [DriveMemClass(range = r
)
279 for r
in drive_sys
.mem_ranges
]
280 for i
in xrange(len(drive_sys
.mem_ctrls
)):
281 drive_sys
.mem_ctrls
[i
].port
= drive_sys
.membus
.master
283 drive_sys
.init_param
= options
.init_param
288 parser
= optparse
.OptionParser()
289 Options
.addCommonOptions(parser
)
290 Options
.addFSOptions(parser
)
292 # Add the ruby specific and protocol specific options
293 if '--ruby' in sys
.argv
:
294 Ruby
.define_options(parser
)
296 (options
, args
) = parser
.parse_args()
299 print("Error: script doesn't take any positional arguments")
302 # system under test can be any CPU
303 (TestCPUClass
, test_mem_mode
, FutureClass
) = Simulation
.setCPUClass(options
)
305 # Match the memories with the CPUs, based on the options for the test system
306 TestMemClass
= Simulation
.setMemClass(options
)
308 if options
.benchmark
:
310 bm
= Benchmarks
[options
.benchmark
]
312 print("Error benchmark %s has not been defined." % options
.benchmark
)
313 print("Valid benchmarks are: %s" % DefinedBenchmarks
)
317 bm
= [SysConfig(disk
=options
.disk_image
, rootdev
=options
.root_device
,
318 mem
=options
.mem_size
, os_type
=options
.os_type
),
319 SysConfig(disk
=options
.disk_image
, rootdev
=options
.root_device
,
320 mem
=options
.mem_size
, os_type
=options
.os_type
)]
322 bm
= [SysConfig(disk
=options
.disk_image
, rootdev
=options
.root_device
,
323 mem
=options
.mem_size
, os_type
=options
.os_type
)]
325 np
= options
.num_cpus
327 test_sys
= build_test_system(np
)
329 drive_sys
= build_drive_system(np
)
330 root
= makeDualRoot(True, test_sys
, drive_sys
, options
.etherdump
)
331 elif len(bm
) == 1 and options
.dist
:
332 # This system is part of a dist-gem5 simulation
333 root
= makeDistRoot(test_sys
,
336 options
.dist_server_name
,
337 options
.dist_server_port
,
338 options
.dist_sync_repeat
,
339 options
.dist_sync_start
,
340 options
.ethernet_linkspeed
,
341 options
.ethernet_linkdelay
,
344 root
= Root(full_system
=True, system
=test_sys
)
346 print("Error I don't know how to create more than 2 systems.")
350 root
.time_sync_enable
= True
352 if options
.frame_capture
:
353 VncServer
.frame_capture
= True
355 if buildEnv
['TARGET_ISA'] == "arm" and not options
.bare_metal \
356 and not options
.dtb_filename
:
357 if options
.machine_type
not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
358 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
359 "platforms, unless custom hardware models have been equipped "\
360 "with generation functionality.")
362 # Generate a Device Tree
363 for sysname
in ('system', 'testsys', 'drivesys'):
364 if hasattr(root
, sysname
):
365 sys
= getattr(root
, sysname
)
366 sys
.generateDtb(m5
.options
.outdir
, '%s.dtb' % sysname
)
368 Simulation
.setWorkCountOptions(test_sys
, options
)
369 Simulation
.run(options
, root
, test_sys
, FutureClass
)