1 # Copyright (c) 2010-2013, 2016 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14 # Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15 # Copyright (c) 2006-2007 The Regents of The University of Michigan
16 # All rights reserved.
18 # Redistribution and use in source and binary forms, with or without
19 # modification, are permitted provided that the following conditions are
20 # met: redistributions of source code must retain the above copyright
21 # notice, this list of conditions and the following disclaimer;
22 # redistributions in binary form must reproduce the above copyright
23 # notice, this list of conditions and the following disclaimer in the
24 # documentation and/or other materials provided with the distribution;
25 # neither the name of the copyright holders nor the names of its
26 # contributors may be used to endorse or promote products derived from
27 # this software without specific prior written permission.
29 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 from __future__
import print_function
50 from m5
.defines
import buildEnv
51 from m5
.objects
import *
52 from m5
.util
import addToPath
, fatal
, warn
53 from m5
.util
.fdthelper
import *
59 from common
.FSConfig
import *
60 from common
.SysPaths
import *
61 from common
.Benchmarks
import *
62 from common
import Simulation
63 from common
import CacheConfig
64 from common
import MemConfig
65 from common
import CpuConfig
66 from common
.Caches
import *
67 from common
import Options
69 def cmd_line_template():
70 if options
.command_line
and options
.command_line_file
:
71 print("Error: --command-line and --command-line-file are "
74 if options
.command_line
:
75 return options
.command_line
76 if options
.command_line_file
:
77 return open(options
.command_line_file
).read().strip()
80 def build_test_system(np
):
81 cmdline
= cmd_line_template()
82 if buildEnv
['TARGET_ISA'] == "alpha":
83 test_sys
= makeLinuxAlphaSystem(test_mem_mode
, bm
[0], options
.ruby
,
85 elif buildEnv
['TARGET_ISA'] == "mips":
86 test_sys
= makeLinuxMipsSystem(test_mem_mode
, bm
[0], cmdline
=cmdline
)
87 elif buildEnv
['TARGET_ISA'] == "sparc":
88 test_sys
= makeSparcSystem(test_mem_mode
, bm
[0], cmdline
=cmdline
)
89 elif buildEnv
['TARGET_ISA'] == "x86":
90 test_sys
= makeLinuxX86System(test_mem_mode
, options
.num_cpus
, bm
[0],
91 options
.ruby
, cmdline
=cmdline
)
92 elif buildEnv
['TARGET_ISA'] == "arm":
93 test_sys
= makeArmSystem(test_mem_mode
, options
.machine_type
,
94 options
.num_cpus
, bm
[0], options
.dtb_filename
,
95 bare_metal
=options
.bare_metal
,
97 ignore_dtb
=options
.generate_dtb
,
99 options
.external_memory_system
,
101 security
=options
.enable_security_extensions
)
102 if options
.enable_context_switch_stats_dump
:
103 test_sys
.enable_context_switch_stats_dump
= True
105 fatal("Incapable of building %s full system!", buildEnv
['TARGET_ISA'])
107 # Set the cache line size for the entire system
108 test_sys
.cache_line_size
= options
.cacheline_size
110 # Create a top-level voltage domain
111 test_sys
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
113 # Create a source clock for the system and set the clock period
114 test_sys
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
115 voltage_domain
= test_sys
.voltage_domain
)
117 # Create a CPU voltage domain
118 test_sys
.cpu_voltage_domain
= VoltageDomain()
120 # Create a source clock for the CPUs and set the clock period
121 test_sys
.cpu_clk_domain
= SrcClockDomain(clock
= options
.cpu_clock
,
123 test_sys
.cpu_voltage_domain
)
125 if options
.kernel
is not None:
126 test_sys
.kernel
= binary(options
.kernel
)
128 if options
.script
is not None:
129 test_sys
.readfile
= options
.script
132 test_sys
.have_lpae
= True
134 if options
.virtualisation
:
135 test_sys
.have_virtualization
= True
137 test_sys
.init_param
= options
.init_param
139 # For now, assign all the CPUs to the same clock domain
140 test_sys
.cpu
= [TestCPUClass(clk_domain
=test_sys
.cpu_clk_domain
, cpu_id
=i
)
143 if CpuConfig
.is_kvm_cpu(TestCPUClass
) or CpuConfig
.is_kvm_cpu(FutureClass
):
144 test_sys
.kvm_vm
= KvmVM()
147 bootmem
= getattr(test_sys
, 'bootmem', None)
148 Ruby
.create_system(options
, True, test_sys
, test_sys
.iobus
,
149 test_sys
._dma
_ports
, bootmem
)
151 # Create a seperate clock domain for Ruby
152 test_sys
.ruby
.clk_domain
= SrcClockDomain(clock
= options
.ruby_clock
,
153 voltage_domain
= test_sys
.voltage_domain
)
155 # Connect the ruby io port to the PIO bus,
156 # assuming that there is just one such port.
157 test_sys
.iobus
.master
= test_sys
.ruby
._io
_port
.slave
159 for (i
, cpu
) in enumerate(test_sys
.cpu
):
161 # Tie the cpu ports to the correct ruby system ports
163 cpu
.clk_domain
= test_sys
.cpu_clk_domain
165 cpu
.createInterruptController()
167 cpu
.icache_port
= test_sys
.ruby
._cpu
_ports
[i
].slave
168 cpu
.dcache_port
= test_sys
.ruby
._cpu
_ports
[i
].slave
170 if buildEnv
['TARGET_ISA'] in ("x86", "arm"):
171 cpu
.itb
.walker
.port
= test_sys
.ruby
._cpu
_ports
[i
].slave
172 cpu
.dtb
.walker
.port
= test_sys
.ruby
._cpu
_ports
[i
].slave
174 if buildEnv
['TARGET_ISA'] in "x86":
175 cpu
.interrupts
[0].pio
= test_sys
.ruby
._cpu
_ports
[i
].master
176 cpu
.interrupts
[0].int_master
= test_sys
.ruby
._cpu
_ports
[i
].slave
177 cpu
.interrupts
[0].int_slave
= test_sys
.ruby
._cpu
_ports
[i
].master
180 if options
.caches
or options
.l2cache
:
181 # By default the IOCache runs at the system clock
182 test_sys
.iocache
= IOCache(addr_ranges
= test_sys
.mem_ranges
)
183 test_sys
.iocache
.cpu_side
= test_sys
.iobus
.master
184 test_sys
.iocache
.mem_side
= test_sys
.membus
.slave
185 elif not options
.external_memory_system
:
186 test_sys
.iobridge
= Bridge(delay
='50ns', ranges
= test_sys
.mem_ranges
)
187 test_sys
.iobridge
.slave
= test_sys
.iobus
.master
188 test_sys
.iobridge
.master
= test_sys
.membus
.slave
191 if options
.simpoint_profile
:
192 if not CpuConfig
.is_atomic_cpu(TestCPUClass
):
193 fatal("SimPoint generation should be done with atomic cpu")
195 fatal("SimPoint generation not supported with more than one CPUs")
198 if options
.simpoint_profile
:
199 test_sys
.cpu
[i
].addSimPointProbe(options
.simpoint_interval
)
201 test_sys
.cpu
[i
].addCheckerCpu()
202 test_sys
.cpu
[i
].createThreads()
204 # If elastic tracing is enabled when not restoring from checkpoint and
205 # when not fast forwarding using the atomic cpu, then check that the
206 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
207 # passes then attach the elastic trace probe.
208 # If restoring from checkpoint or fast forwarding, the code that does this for
209 # FutureCPUClass is in the Simulation module. If the check passes then the
210 # elastic trace probe is attached to the switch CPUs.
211 if options
.elastic_trace_en
and options
.checkpoint_restore
== None and \
212 not options
.fast_forward
:
213 CpuConfig
.config_etrace(TestCPUClass
, test_sys
.cpu
, options
)
215 CacheConfig
.config_cache(options
, test_sys
)
217 MemConfig
.config_mem(options
, test_sys
)
221 def build_drive_system(np
):
222 # driver system CPU is always simple, so is the memory
223 # Note this is an assignment of a class, not an instance.
224 DriveCPUClass
= AtomicSimpleCPU
225 drive_mem_mode
= 'atomic'
226 DriveMemClass
= SimpleMemory
228 cmdline
= cmd_line_template()
229 if buildEnv
['TARGET_ISA'] == 'alpha':
230 drive_sys
= makeLinuxAlphaSystem(drive_mem_mode
, bm
[1], cmdline
=cmdline
)
231 elif buildEnv
['TARGET_ISA'] == 'mips':
232 drive_sys
= makeLinuxMipsSystem(drive_mem_mode
, bm
[1], cmdline
=cmdline
)
233 elif buildEnv
['TARGET_ISA'] == 'sparc':
234 drive_sys
= makeSparcSystem(drive_mem_mode
, bm
[1], cmdline
=cmdline
)
235 elif buildEnv
['TARGET_ISA'] == 'x86':
236 drive_sys
= makeLinuxX86System(drive_mem_mode
, np
, bm
[1],
238 elif buildEnv
['TARGET_ISA'] == 'arm':
239 drive_sys
= makeArmSystem(drive_mem_mode
, options
.machine_type
, np
,
240 bm
[1], options
.dtb_filename
, cmdline
=cmdline
,
241 ignore_dtb
=options
.generate_dtb
)
243 # Create a top-level voltage domain
244 drive_sys
.voltage_domain
= VoltageDomain(voltage
= options
.sys_voltage
)
246 # Create a source clock for the system and set the clock period
247 drive_sys
.clk_domain
= SrcClockDomain(clock
= options
.sys_clock
,
248 voltage_domain
= drive_sys
.voltage_domain
)
250 # Create a CPU voltage domain
251 drive_sys
.cpu_voltage_domain
= VoltageDomain()
253 # Create a source clock for the CPUs and set the clock period
254 drive_sys
.cpu_clk_domain
= SrcClockDomain(clock
= options
.cpu_clock
,
256 drive_sys
.cpu_voltage_domain
)
258 drive_sys
.cpu
= DriveCPUClass(clk_domain
=drive_sys
.cpu_clk_domain
,
260 drive_sys
.cpu
.createThreads()
261 drive_sys
.cpu
.createInterruptController()
262 drive_sys
.cpu
.connectAllPorts(drive_sys
.membus
)
263 if options
.kernel
is not None:
264 drive_sys
.kernel
= binary(options
.kernel
)
266 if CpuConfig
.is_kvm_cpu(DriveCPUClass
):
267 drive_sys
.kvm_vm
= KvmVM()
269 drive_sys
.iobridge
= Bridge(delay
='50ns',
270 ranges
= drive_sys
.mem_ranges
)
271 drive_sys
.iobridge
.slave
= drive_sys
.iobus
.master
272 drive_sys
.iobridge
.master
= drive_sys
.membus
.slave
274 # Create the appropriate memory controllers and connect them to the
276 drive_sys
.mem_ctrls
= [DriveMemClass(range = r
)
277 for r
in drive_sys
.mem_ranges
]
278 for i
in xrange(len(drive_sys
.mem_ctrls
)):
279 drive_sys
.mem_ctrls
[i
].port
= drive_sys
.membus
.master
281 drive_sys
.init_param
= options
.init_param
286 parser
= optparse
.OptionParser()
287 Options
.addCommonOptions(parser
)
288 Options
.addFSOptions(parser
)
290 # Add the ruby specific and protocol specific options
291 if '--ruby' in sys
.argv
:
292 Ruby
.define_options(parser
)
294 (options
, args
) = parser
.parse_args()
297 print("Error: script doesn't take any positional arguments")
300 # system under test can be any CPU
301 (TestCPUClass
, test_mem_mode
, FutureClass
) = Simulation
.setCPUClass(options
)
303 # Match the memories with the CPUs, based on the options for the test system
304 TestMemClass
= Simulation
.setMemClass(options
)
306 if options
.benchmark
:
308 bm
= Benchmarks
[options
.benchmark
]
310 print("Error benchmark %s has not been defined." % options
.benchmark
)
311 print("Valid benchmarks are: %s" % DefinedBenchmarks
)
315 bm
= [SysConfig(disk
=options
.disk_image
, rootdev
=options
.root_device
,
316 mem
=options
.mem_size
, os_type
=options
.os_type
),
317 SysConfig(disk
=options
.disk_image
, rootdev
=options
.root_device
,
318 mem
=options
.mem_size
, os_type
=options
.os_type
)]
320 bm
= [SysConfig(disk
=options
.disk_image
, rootdev
=options
.root_device
,
321 mem
=options
.mem_size
, os_type
=options
.os_type
)]
323 np
= options
.num_cpus
325 test_sys
= build_test_system(np
)
327 drive_sys
= build_drive_system(np
)
328 root
= makeDualRoot(True, test_sys
, drive_sys
, options
.etherdump
)
329 elif len(bm
) == 1 and options
.dist
:
330 # This system is part of a dist-gem5 simulation
331 root
= makeDistRoot(test_sys
,
334 options
.dist_server_name
,
335 options
.dist_server_port
,
336 options
.dist_sync_repeat
,
337 options
.dist_sync_start
,
338 options
.ethernet_linkspeed
,
339 options
.ethernet_linkdelay
,
342 root
= Root(full_system
=True, system
=test_sys
)
344 print("Error I don't know how to create more than 2 systems.")
348 root
.time_sync_enable
= True
350 if options
.frame_capture
:
351 VncServer
.frame_capture
= True
353 if buildEnv
['TARGET_ISA'] == "arm" and options
.generate_dtb
:
355 if options
.dtb_filename
:
356 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
359 if options
.machine_type
not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
360 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
361 "platforms, unless custom hardware models have been equipped "\
362 "with generation functionality.")
364 # Generate a Device Tree
365 def create_dtb_for_system(system
, filename
):
366 state
= FdtState(addr_cells
=2, size_cells
=2, cpu_cells
=1)
367 rootNode
= system
.generateDeviceTree(state
)
370 fdt
.add_rootnode(rootNode
)
371 dtb_filename
= os
.path
.join(m5
.options
.outdir
, filename
)
372 return fdt
.writeDtbFile(dtb_filename
)
374 for sysname
in ('system', 'testsys', 'drivesys'):
375 if hasattr(root
, sysname
):
376 sys
= getattr(root
, sysname
)
377 sys
.dtb_filename
= create_dtb_for_system(sys
, '%s.dtb' % sysname
)
379 Simulation
.setWorkCountOptions(test_sys
, options
)
380 Simulation
.run(options
, root
, test_sys
, FutureClass
)