1 # Copyright (c) 2010 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
14 # All rights reserved.
16 # Redistribution and use in source and binary forms, with or without
17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
19 # notice, this list of conditions and the following disclaimer;
20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
22 # documentation and/or other materials provided with the distribution;
23 # neither the name of the copyright holders nor the names of its
24 # contributors may be used to endorse or promote products derived from
25 # this software without specific prior written permission.
27 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
46 from m5
.defines
import buildEnv
47 from m5
.objects
import *
48 from m5
.util
import addToPath
, fatal
50 if not buildEnv
['FULL_SYSTEM']:
51 fatal("This script requires full-system mode (*_FS).")
53 addToPath('../common')
55 from FSConfig
import *
56 from SysPaths
import *
57 from Benchmarks
import *
62 # Get paths we might need. It's expected this file is in m5/configs/example.
63 config_path
= os
.path
.dirname(os
.path
.abspath(__file__
))
64 config_root
= os
.path
.dirname(config_path
)
66 parser
= optparse
.OptionParser()
69 parser
.add_option("--timesync", action
="store_true",
70 help="Prevent simulated time from getting ahead of real time")
73 parser
.add_option("--kernel", action
="store", type="string")
74 parser
.add_option("--script", action
="store", type="string")
75 if buildEnv
['TARGET_ISA'] == "arm":
76 parser
.add_option("--bare-metal", action
="store_true",
77 help="Provide the raw system without the linux specific bits")
78 parser
.add_option("--machine-type", action
="store", type="choice",
79 choices
=ArmMachineType
.map.keys(), default
="RealView_PBX")
81 parser
.add_option("--dual", action
="store_true",
82 help="Simulate two systems attached with an ethernet link")
83 parser
.add_option("-b", "--benchmark", action
="store", type="string",
85 help="Specify the benchmark to run. Available benchmarks: %s"\
89 parser
.add_option("--etherdump", action
="store", type="string", dest
="etherdump",
90 help="Specify the filename to dump a pcap capture of the" \
93 execfile(os
.path
.join(config_root
, "common", "Options.py"))
95 (options
, args
) = parser
.parse_args()
98 print "Error: script doesn't take any positional arguments"
101 # driver system CPU is always simple... note this is an assignment of
102 # a class, not an instance.
103 DriveCPUClass
= AtomicSimpleCPU
104 drive_mem_mode
= 'atomic'
106 # system under test can be any CPU
107 (TestCPUClass
, test_mem_mode
, FutureClass
) = Simulation
.setCPUClass(options
)
109 TestCPUClass
.clock
= '2GHz'
110 DriveCPUClass
.clock
= '2GHz'
112 if options
.benchmark
:
114 bm
= Benchmarks
[options
.benchmark
]
116 print "Error benchmark %s has not been defined." % options
.benchmark
117 print "Valid benchmarks are: %s" % DefinedBenchmarks
121 bm
= [SysConfig(), SysConfig()]
125 np
= options
.num_cpus
127 if buildEnv
['TARGET_ISA'] == "alpha":
128 test_sys
= makeLinuxAlphaSystem(test_mem_mode
, bm
[0])
129 elif buildEnv
['TARGET_ISA'] == "mips":
130 test_sys
= makeLinuxMipsSystem(test_mem_mode
, bm
[0])
131 elif buildEnv
['TARGET_ISA'] == "sparc":
132 test_sys
= makeSparcSystem(test_mem_mode
, bm
[0])
133 elif buildEnv
['TARGET_ISA'] == "x86":
134 test_sys
= makeLinuxX86System(test_mem_mode
, np
, bm
[0])
135 elif buildEnv
['TARGET_ISA'] == "arm":
136 test_sys
= makeLinuxArmSystem(test_mem_mode
, bm
[0],
137 bare_metal
=options
.bare_metal
, machine_type
=options
.machine_type
)
139 fatal("incapable of building non-alpha or non-sparc full system!")
141 if options
.kernel
is not None:
142 test_sys
.kernel
= binary(options
.kernel
)
144 if options
.script
is not None:
145 test_sys
.readfile
= options
.script
147 test_sys
.cpu
= [TestCPUClass(cpu_id
=i
) for i
in xrange(np
)]
149 CacheConfig
.config_cache(options
, test_sys
)
151 if options
.caches
or options
.l2cache
:
153 mem_size
= bm
[0].mem()
155 mem_size
= SysConfig().mem()
156 test_sys
.bridge
.filter_ranges_a
=[AddrRange(0, Addr
.max)]
157 test_sys
.bridge
.filter_ranges_b
=[AddrRange(mem_size
)]
158 test_sys
.iocache
= IOCache(addr_range
=mem_size
)
159 test_sys
.iocache
.cpu_side
= test_sys
.iobus
.port
160 test_sys
.iocache
.mem_side
= test_sys
.membus
.port
164 test_sys
.cpu
[i
].physmem_port
= test_sys
.physmem
.port
166 if buildEnv
['TARGET_ISA'] == 'mips':
167 setMipsOptions(TestCPUClass
)
170 if buildEnv
['TARGET_ISA'] == 'alpha':
171 drive_sys
= makeLinuxAlphaSystem(drive_mem_mode
, bm
[1])
172 elif buildEnv
['TARGET_ISA'] == 'mips':
173 drive_sys
= makeLinuxMipsSystem(drive_mem_mode
, bm
[1])
174 elif buildEnv
['TARGET_ISA'] == 'sparc':
175 drive_sys
= makeSparcSystem(drive_mem_mode
, bm
[1])
176 elif buildEnv
['TARGET_ISA'] == 'x86':
177 drive_sys
= makeX86System(drive_mem_mode
, np
, bm
[1])
178 elif buildEnv
['TARGET_ISA'] == 'arm':
179 drive_sys
= makeLinuxArmSystem(drive_mem_mode
, bm
[1])
180 drive_sys
.cpu
= DriveCPUClass(cpu_id
=0)
181 drive_sys
.cpu
.connectMemPorts(drive_sys
.membus
)
183 drive_sys
.cpu
.physmem_port
= drive_sys
.physmem
.port
184 if options
.kernel
is not None:
185 drive_sys
.kernel
= binary(options
.kernel
)
187 root
= makeDualRoot(test_sys
, drive_sys
, options
.etherdump
)
189 root
= Root(system
=test_sys
)
191 print "Error I don't know how to create more than 2 systems."
195 root
.time_sync_enable
= True
197 Simulation
.run(options
, root
, test_sys
, FutureClass
)