1 # Copyright (c) 2017, University of Kaiserslautern
4 # Redistribution and use in source and binary forms, with or without
5 # modification, are permitted provided that the following conditions are
8 # 1. Redistributions of source code must retain the above copyright notice,
9 # this list of conditions and the following disclaimer.
11 # 2. Redistributions in binary form must reproduce the above copyright
12 # notice, this list of conditions and the following disclaimer in the
13 # documentation and/or other materials provided with the distribution.
15 # 3. Neither the name of the copyright holder nor the names of its
16 # contributors may be used to endorse or promote products derived from
17 # this software without specific prior written permission.
19 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 # TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 # PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
23 # OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 # PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 # PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 # LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 # Author: Éder F. Zulian
33 from __future__
import print_function
34 from __future__
import absolute_import
40 from m5
.objects
import *
43 from common
import MemConfig
44 from common
import HMC
47 pd
= "Simple 'hello world' example using HMC as main memory"
48 parser
= argparse
.ArgumentParser(description
=pd
)
49 HMC
.add_options(parser
)
50 options
= parser
.parse_args()
51 # create the system we are going to simulate
53 # use timing mode for the interaction between master-slave ports
54 system
.mem_mode
= 'timing'
55 # set the clock fequency of the system
57 vd
= VoltageDomain(voltage
='1V')
58 system
.clk_domain
= SrcClockDomain(clock
=clk
, voltage_domain
=vd
)
60 system
.cpu
= TimingSimpleCPU()
61 # config memory system
62 MemConfig
.config_mem(options
, system
)
63 # hook the CPU ports up to the membus
64 system
.cpu
.icache_port
= system
.membus
.slave
65 system
.cpu
.dcache_port
= system
.membus
.slave
66 # create the interrupt controller for the CPU and connect to the membus
67 system
.cpu
.createInterruptController()
68 # connect special port in the system to the membus. This port is a
69 # functional-only port to allow the system to read and write memory.
70 system
.system_port
= system
.membus
.slave
71 # get ISA for the binary to run.
72 isa
= str(m5
.defines
.buildEnv
['TARGET_ISA']).lower()
73 # run 'hello' and use the compiled ISA to find the binary
74 binary
= 'tests/test-progs/hello/bin/' + isa
+ '/linux/hello'
75 # create a process for a simple "Hello World" application
77 # cmd is a list which begins with the executable (like argv)
78 process
.cmd
= [binary
]
79 # set the cpu workload
80 system
.cpu
.workload
= process
81 # create thread contexts
82 system
.cpu
.createThreads()
83 # set up the root SimObject
84 root
= Root(full_system
=False, system
=system
)