6 from m5
.objects
import *
7 from m5
.util
import addToPath
11 from common
import MemConfig
12 from common
import HMC
14 parser
= optparse
.OptionParser()
16 # Use a HMC_2500_1x32 (1 channel, 32-bits wide) by default
17 parser
.add_option("--mem-type", type = "choice", default
= "HMC_2500_1x32",
18 choices
= MemConfig
.mem_names(),
19 help = "type of memory to use")
21 parser
.add_option("--ranks", "-r", type = "int", default
= 1,
22 help = "Number of ranks to iterate across")
24 parser
.add_option("--rd_perc", type ="int", default
=100,
25 help = "Percentage of read commands")
27 parser
.add_option("--mode", type ="choice", default
="DRAM",
28 choices
= ["DRAM", "DRAM_ROTATE", "RANDOM"],
29 help = "DRAM: Random traffic; \
30 DRAM_ROTATE: Traffic rotating across banks and ranks"
33 parser
.add_option("--addr_map", type ="int", default
= 1,
34 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo")
36 parser
.add_option("--arch", type = "choice", default
= "distributed",
37 choices
= ["same", "distributed", "mixed"],
38 help = "same: HMC-4 links with same range\
39 distributed: HMC-4 links with distributed range\
40 mixed: mixed with same & distributed range")
42 parser
.add_option("--linkaggr", type = "int", default
= 0,
43 help = "1: enable link crossbar, 0: disable link crossbar")
45 parser
.add_option("--num_cross", type = "int", default
= 4,
46 help = "1: number of crossbar in HMC=1;\
47 4: number of crossbar = 4")
49 parser
.add_option("--tlm-memory", type = "string",
50 help="use external port for SystemC TLM cosimulation")
52 parser
.add_option("--elastic-trace-en", action
="store_true",
53 help = """Enable capture of data dependency and instruction
54 fetch traces using elastic trace probe.""")
56 (options
, args
) = parser
.parse_args()
59 print "Error: script doesn't take any positional arguments"
63 system
.clk_domain
= SrcClockDomain(clock
='100GHz',
65 VoltageDomain(voltage
= '1V'))
66 # Create additional crossbar for arch1
67 if options
.arch
== "distributed" or options
.arch
== "mixed" :
68 system
.membus
= NoncoherentXBar( width
=8 )
69 system
.membus
.badaddr_responder
= BadAddr()
70 system
.membus
.default
= Self
.badaddr_responder
.pio
71 system
.membus
.width
= 8
72 system
.membus
.frontend_latency
= 3
73 system
.membus
.forward_latency
= 4
74 system
.membus
.response_latency
= 2
76 system
.membus
.clk_domain
= SrcClockDomain(clock
='100GHz', voltage_domain
=
77 VoltageDomain(voltage
= '1V'))
79 # we are considering 4GB HMC device with following parameters
80 # hmc_device_size = '4GB'
82 # hmc_vault_size = '256MB'
84 # hmc_bank_in_stack = 2
85 # hmc_bank_size = '16MB'
86 # hmc_bank_in_vault = 16
88 # determine the burst length in bytes
92 options
.mem_channels
= 1
93 options
.external_memory_system
= 0
95 stride_size
= burst_size
96 system
.cache_line_size
= burst_size
98 # Enable performance monitoring
99 options
.enable_global_monitor
= True
100 options
.enable_link_monitor
= False
102 # Bytes used for calculations
103 oneGBytes
= 1024 * 1024 * 1024
104 oneMBytes
= 1024 * 1024
106 # Memory ranges of 16 vault controller - Total_HMC_size / 16
107 mem_range_vault
= [ AddrRange(i
* 256 * oneMBytes
, ((i
+ 1) * 256 * oneMBytes
)
109 for i
in range(num_vault_ctrl
)]
111 # Memmory ranges of serial link for arch-0
112 # Same as the ranges of vault controllers - 4 vault - to - 1 serial link
113 if options
.arch
== "same":
114 ser_range
= [ AddrRange(0, (4 * oneGBytes
) - 1)
115 for i
in range(num_serial_links
)]
116 options
.ser_ranges
= ser_range
118 # Memmory ranges of serial link for arch-1
119 # Distributed range accross links
120 if options
.arch
== "distributed":
121 ser_range
= [ AddrRange(i
* oneGBytes
, ((i
+ 1) * oneGBytes
) - 1)
122 for i
in range(num_serial_links
)]
123 options
.ser_ranges
= ser_range
125 # Memmory ranges of serial link for arch-2
126 # "Mixed" address distribution over links
127 if options
.arch
== "mixed":
128 ser_range0
= AddrRange(0 , (1 * oneGBytes
) - 1)
129 ser_range1
= AddrRange(1 * oneGBytes
, (2 * oneGBytes
) - 1)
130 ser_range2
= AddrRange(0 , (4 * oneGBytes
) - 1)
131 ser_range3
= AddrRange(0 , (4 * oneGBytes
) - 1)
132 options
.ser_ranges
= [ser_range0
, ser_range1
, ser_range2
, ser_range3
]
134 # Assign ranges of vault controller to system ranges
135 system
.mem_ranges
= mem_range_vault
137 # open traffic generator
138 cfg_file_name
= "./tests/quick/se/70.tgen/traffic.cfg"
139 cfg_file
= open(cfg_file_name
, 'r')
141 # number of traffic generator
143 # create a traffic generator, and point it to the file we just created
144 system
.tgen
= [ TrafficGen(config_file
= cfg_file_name
) for i
in xrange(np
)]
146 # Config memory system with given HMC arch
147 MemConfig
.config_mem(options
, system
)
149 if options
.arch
== "distributed":
151 system
.tgen
[i
].port
= system
.membus
.slave
152 # connect the system port even if it is not used in this example
153 system
.system_port
= system
.membus
.slave
155 if options
.arch
== "mixed":
156 for i
in xrange(int(np
/2)):
157 system
.tgen
[i
].port
= system
.membus
.slave
158 # connect the system port even if it is not used in this example
159 system
.system_port
= system
.membus
.slave
163 root
= Root(full_system
= False, system
= system
)
164 root
.system
.mem_mode
= 'timing'
167 m5
.simulate(10000000000)